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参数资料
| 型号： | LTC4215CUFD-2#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 15/28页 |
| 文件大小： | 265K |
| 描述： | IC CTRLR HOT SWAP 24-QFN |
| 标准包装： | 73 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 2.9 V ~ 15 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（5x4） |
| 包装： | 管件 |
| 产品目录页面： | 1342 (CN2011-ZH PDF) |
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LTC4215/LTC4215-2
15
4215fe
APPLICATIONS INFORMATION
If a connection sense on the plug-in card is driving the EN
pin, insertion or removal of the card may cause the pin
voltage to bounce. This results in clearing the fault register
when the card is removed. The pin may be debounced
using a lter capacitor, C
EN
, on the ENpin as shown in
Figure 4. The lter time is given by:
t
FILTER
= C
EN
" 123 [ms/糉]
Fault Alerts
When any of the fault bits in FAULT register D are set, an
optional bus alert is generated if the appropriate bit in the
ALERT register B has been set. This allows only selected
faults to generate alerts. At power-up the default state is to
not alert on faults. If an alert is enabled, the correspond-
ing fault causes the ALERT pin to pull low. After the bus
master controller broadcasts the Alert Response Address,
the LTC4215 responds with its address on the SDA line and
releases ALERT as shown in Table 6. If there is a collision
between two LTC4215s responding with their addresses
simultaneously, then the device with the lower address
wins arbitration and responds rst. The ALERT line is also
released if the device is addressed by the bus master.
Once the ALERT signal has been released for one fault, it
is not pulled low again until the FAULT register indicates a
different fault has occurred or the original fault is cleared
and it occurs again. Note that this means repeated or
continuing faults do not generate alerts until the associ-
ated FAULT register bit has been cleared.
Resetting Faults
Faults are reset with any of the following conditions. First,
a serial bus command writing zeros to the FAULT register
D clears the associated faults. Second, the entire FAULT
register is cleared when the switch is turned off by the ON
pin or bit A3 going from high to low, if the UV pin is brought
below its 0.4V reset threshold for 2約, or if INTV
CC
falls
below its 2.64V undervoltage lockout threshold. Finally,
when EN is brought from high to low, only FAULT bits
D0-D3 are cleared, and bit D4, that indicates a EN change
of state, is set. Note that faults that are still present, as
indicated in STATUS Register C, cannot be cleared.
The FAULT register is not cleared when auto-retrying.
When auto-retry is disabled the existence of a D0, D1
or D2 fault keeps the switch off. As soon as the fault is
cleared, the switch turns on. If auto-retry is enabled, then
a high value in C0, C1 or C2 holds the switch off and the
fault register is ignored. Subsequently, when bits C0, C1
+
1.235V
GND
MOTHERBOARD
CONNECTOR
PLUG-IN
CARD
SOURCE
OUT
LTC4215
EN
C
EN
LOAD
4215 F04
10糀
Figure 4. Plug-In Card Insertion/Removal
FET Short Fault
A FET short fault is reported if the data converter measures
a current sense voltage greater than or equal to 1.6mV
while the GATE is turned off. This condition sets FET short
present bit, C5, and FET short fault bit D5.
Power Bad Fault
A power bad fault is reported if the FB pin voltage drops
below its 1.235V threshold for more than 2約 when the
GATE is high. This pulls the GPIO pin low immediately
when con gured as power-good, and sets power-bad
present bit, C3, and power bad fault bit D3. A circuit pre-
vents power-bad faults if the GATE-to-SOURCE voltage is
low, eliminating false power-bad faults during power-up
or power-down. If the FB pin voltage subsequently rises
back above the threshold, the GPIO pin returns to a high
impedance state and bit C3 is reset.
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