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参数资料
| 型号： | LTC4222CUH#TRPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC32 |
| 封装： | 5 X 5 MM, LEAD FREE, PLASTIC, MO-220WHHD-X, QFN-32 |
| 文件页数： | 11/32页 |
| 文件大小： | 280K |
| 代理商： | LTC4222CUH#TRPBF |
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LTC4222
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APPLICATIONS INFORMATION
Conguring the GPIO Pins
Table 3 describes the possible states of the GPIO pins using
the CONTROL registers bits 6 and 7. At power-up, the default
state is for a GPIO pin to go high impedance when power is
good (FB pin greater than 1.235V). Other applications for a
GPIO pin are to pull down when power is good, a general
purpose output and a general purpose input.
A simple application of the GPIO pin in the power good
conguration is to connect it to the UV pin of the other
channel with the CONFIG pin high. This will result in the
second channel being turned on after the rst channel has
started up and signaled power good.
Current Limit Stability
For many applications the LTC4222 current limit will be
stable without additional components. However there are
certain conditions where additional components may be
needed to improve stability. The dominant pole of the cur-
rent limit circuit is set by the capacitance and resistance at
the gate of the external MOSFET, and larger gate capaci-
tance makes the current limit loop more stable. Usually
a total of 8nF gate to source capacitance is sufcient for
stability and is typically provided by inherent MOSFET CGS,
however the stability of the loop is degraded by increasing
RSENSE or by reducing the size of the resistor on a gate RC
network if one is used, which may require additional gate
to source capacitance. Board level short-circuit testing
is highly recommended as board layout can also affect
transient performance, for stability testing the worst-case
condition for current limit stability occurs when the output
is shorted to ground after a normal start-up.
There are two possible parasitic oscillations when the
MOSFET operates as a source follower when ramping
at power-up or during current limiting. The rst type of
oscillation occurs at high frequencies, typically above
1MHz. This high frequency oscillation is easily damped
with R5 as shown in Figure 1. In some applications, one
may nd that R5 helps in short-circuit transient recovery
as well. However, too large of an R5 value will slow down
the turn-off time. The recommended R5 range is between
5Ω and 500Ω.
The second type of source follower oscillation occurs at
frequencies between 200kHz and 800kHz due to the load
capacitance being between 0.2μF and 9μF, the presence
of R5 resistance, the absence of a drain bypass capacitor,
a combination of bus wiring inductance and bus supply
output impedance. To prevent this second type of oscillation
avoid load capacitance below 10μF, alternately connect an
external capacitor from the MOSFET gate to ground with
a value greater than 1.5nF.
Supply Transients
The LTC4222 is designed to ride through supply transients
caused by load steps. If there is a shorted load and the
parasitic inductance back to the supply is greater than
0.5μH, there is a chance that the supply collapses before
the active current limit circuit brings down the GATE pin.
If this occurs, the undervoltage monitors pull the corre-
sponding GATE pin low. The undervoltage lockout circuit
has a 2μs lter time after VDD drops below 2.35V. The UV
pin reacts in 2μs to shut the GATE off, but it is recom-
mended to add a lter capacitor, CF, to prevent unwanted
shutdown caused by a transient. Eventually either the UV
pin or undervoltage lockout responds to bring the current
under control before the supply completely collapses.
Supply Transient Protection
The LTC4222 is safe from damage with supply voltages up
to 35V. However, spikes above 35V may damage the part.
During a short-circuit condition, large changes in current
owing through power supply traces may cause induc-
tive voltage spikes which exceed 35V. To minimize such
spikes, the power trace inductance should be minimized
by using wider traces or heavier trace plating. Also, a
snubber circuit dampens inductive voltage spikes. Build
a snubber by using a 100Ω resistor in series with a 0.1μF
capacitor between VDD and GND. A surge suppressor, Z1
in Figure 1, at the input can also prevent damage from
voltage surges.
Design Example
As a design example, take the following specications for
channel 1: VIN = 12V, IMAX = 5A, IINRUSH = 1A, dI/dtINRUSH
= 10A/ms, CL = 330μF, VUV(RISING) = 10.75V, VOV(FALLING)
= 14.0V, VPWRGD(UP)=11.6V,andI2CADDRESS=1000111.
This completed design is shown in Figure 1.
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| LTC4222IG#TRPBF | 功能描述:IC CTRLR DUAL HOT SWAP 36-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF) |
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