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| 型号： | LTC4225IGN-1#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 15/24页 |
| 文件大小： | 346K |
| 描述： | IC CTLR HOT SWAP DUAL 24-SSOP |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电流限制： | 可调 |
| 电源电压： | 2.9 V ~ 18 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 带卷 (TR) |
LTC4225-1/LTC4225-2
15
422512f
MOSFET Selection
The LTC4225 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
on-resistance, R
DS(ON)
, the maximum drain-source volt-
age, BV
DSS
, and the threshold voltage.
The gate drive for the ideal diode MOSFET and Hot Swap
MOSFET is guaranteed to be greater than 5V and 4.8V
respectively when the supply voltages at IN1 and IN2 are
between 2.9V and 7V . When the supply voltages at IN1 and
IN2 are greater than 7V , the gate drive is guaranteed to be
greater than 10V . The gate drive is limited to not more than
14V . This allows the use of logic-level threshold N-channel
MOSFETs and standard N-channel MOSFETs above 7V . An
external Zener diode can be used to clamp the potential
from the MOSFETs gate to source if the rated breakdown
voltage is less than 14V .
The maximum allowable drain-source voltage, BV
DSS
,
must be higher than the supply voltages as the full sup-
ply voltage can appear across the MOSFET . If an input or
output is connected to ground, the full supply voltage will
appear across the MOSFET . The R
DS(ON)
should be small
enough to conduct the maximum load current, and also
stay within the MOSFET s power rating.
CPO Capacitor Selection
The recommended value of the capacitor, C
CP
, between the
CPO and IN pins is approximately 10?the input capaci-
tance, C
ISS
, of the ideal diode MOSFET . A larger capacitor
takes a correspondingly longer time to charge up by the
internal charge pump. A smaller capacitor suffers more
voltage drop during a fast gate turn-on event as it shares
charge with the MOSFET gate capacitance.
Supply Transient Protection
When the capacitances at the input and output are very
small, rapid changes in current during input or output short-
circuit events can cause transients that exceed the 24V
absolute maximum ratings of the IN and OUT pins. To mini-
mize such spikes, use wider traces or heavier trace plating
to reduce the power trace inductance. Also, bypass locally
with a 10礔 electrolytic and 0.1礔 ceramic, or alternatively
clamp the input with a transient voltage suppressor (Z1, Z2).
A 10? 0.1礔 snubber damps the response and eliminates
ringing (See Figure 11).
Design Example
As a design example for selecting components, consider
a 12V system with a 7.6A maximum load current for the
two supplies (see Figure 1).
First, select the appropriate value of the current sense
resistors (R
S1
and R
S2
) for the 12V supply. Calculate
the sense resistor value based on the maximum load
current I
LOAD(MAX)
, the minimum circuit breaker trip cur-
rent I
TRIP(MIN)
and the lower limit for the circuit breaker
threshold V
SENSE(CB)(MIN)
. A load current margin given
as a ratio of I
TRIP(MIN)
/I
LOAD(MAX)
is provided for allowing
backfeeding current to flow through the sense resistor
momentarily, without false tripping the circuit breaker on
the higher supply before the reverse turn-off is activated on
the lower supply. Assuming a load current margin of 1.5?
I
TRIP(MIN)
= 1.5 " I
LOAD(MAX)
= 1.5 " 7.6A = 11.4A
R
S
=
V
SENSE(CB)(MIN)
I
TRIP(MIN)
=
47.5mV
11.4A
= 4.16m&
Choose a 4m?sense resistor with a 1% tolerance.
Next, calculate the R
DS(ON)
of the MOSFET to achieve
the desired forward drop at maximum load. Assuming a
forward drop, V
FWD
of 60mV across the two MOSFETs
connected back-to-back:
R
DS(ON,TOTAL)
d
V
FWD
I
LOAD(MAX)
=
60mV
7.6A
=7.9m&
The Si7336ADP offers a good choice with a maximum
R
DS(ON)
of 3m?at V
GS
= 10V , thereby giving a total of
6m?for two MOSFETs in the supply path. The input ca-
pacitance, C
ISS
, of the Si7336ADP is about 5600pF . Slightly
exceeding the 10?recommendation, a 0.1礔 capacitor is
selected for C
CP1
and C
CP2
at the CPO pins.
applicaTions inForMaTion
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| LTC4225IGN-2#PBF | 功能描述:IC CONTROLLER HOT SWAP 24-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF) |
| LTC4225IGN-2#TRPBF | 功能描述:IC CTLR HOT SWAP DUAL 24-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF) |
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| LTC4225IUFD-1#TRPBF | 功能描述:IC CTLR HOT SWAP DUAL 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF) |
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