参数资料
型号: LTC4227CGN-1#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 电源管理
英文描述: POWER SUPPLY MANAGEMENT CKT, PDSO16
封装: 0.150 INCH, LEAD FREE, PLASTIC, SSOP-16
文件页数: 6/20页
文件大小: 307K
代理商: LTC4227CGN-1#PBF
LTC4227-1/LTC4227-2
14
422712f
applicaTions inForMaTion
There is a 10s glitch filter on the ON pin to reject supply
glitches. By placing a filter capacitor, CF, with the resistive
dividerattheONpin,theglitchfilterdelayisfurtherextended
by the RC time constant to prevent any false fault.
Power Good Monitor
Internal circuitry monitors the MOSFET gate overdrive
between the HGATE and OUT pins. The power good sta-
tus for the supply is reported via the open-drain output,
PWRGD. It is normally pulled high by an external pull-up
resistor or the internal 10A pull-up. The power good
output asserts low when the gate overdrive exceeds 4.2V
during the HGATE start-up. Once asserted low, the power
good status is latched and can only be cleared by pulling
the ON pin low, toggling the EN pin from low to high, or
INTVCC entering undervoltage lockout. The power good
output continues to pull low while HGATE is regulating in
active current limit, but pulls high when the circuit breaker
times out and pulls the HGATE pin low.
CPO and DGATE Start-Up
The CPO and DGATE pin voltages are initially pulled up to a
diode below the IN pin when first powered up. CPO starts
rampingup7safterINTVCCclearsitsundervoltagelockout
level. Another 40s later, DGATE also starts ramping up
with CPO. The CPO ramp rate is determined by the CPO
pull-up current into the combined CPO and DGATE pin
capacitances. An internal clamp limits the CPO pin voltage
to 12V above the IN pin, while the final DGATE pin voltage
is determined by the gate drive amplifier. An internal 12V
clamp limits the DGATE pin voltage above IN.
MOSFET Selection
The LTC4227 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
on-resistance, RDS(ON), the maximum drain-source volt-
age, BVDSS, and the threshold voltage.
The gate drive for the ideal diode MOSFET and Hot Swap
MOSFET is guaranteed to be greater than 5V and 4.8V
respectively when the supply voltages at IN1 and IN2 are
between 2.9V and 7V. When the supply voltages at IN1 and
IN2 are greater than 7V, the gate drive is guaranteed to be
Figure 6. Auto-Retry Sequence After a Fault
Supply Undervoltage Monitor
The ON pin functions as a turn-on control and an input
supply monitor. A resistive divider connected between
the supply diode-OR output (SENSE+) and GND at the
ON pin monitors the supply undervoltage condition. The
undervoltage threshold is set by proper selection of the
resistors, and is given by:
VIN(UVTH) = 1+
R2
R1
VON(TH)
where VON(TH) is the ON rising threshold (1.235V).
Anundervoltagefaultoccursifthediode-ORoutputsupply
fallsbelowitsundervoltagethresholdforlongerthan20s.
The FAULT pin will not be pulled low. If the ON pin voltage
falls below 1.155V but remains above 0.6V, the Hot Swap
MOSFET is turned off by a 300A pull-down from HGATE
to ground. The Hot Swap MOSFET turns back on instantly
without the 100ms debounce cycle when the diode-OR
output supply rises above its undervoltage threshold.
However, if the ON pin voltage drops below 0.6V, it turns off
the Hot Swap MOSFET and clears the fault latches. The Hot
Swap MOSFET turns back on only after a 100ms debounce
cycle when the diode-OR output supply is restored above
its undervoltage threshold. The ideal diode MOSFETs are
not affected by the undervoltage fault conditions.
If both IN supplies fall until the internally generated sup-
ply, INTVCC, drops below its 2.2V UVLO threshold, all the
MOSFETs are turned off and the fault latches are cleared.
Operation resumes from a fresh start-up cycle when the
input supplies are restored and INTVCC exceeds its UVLO
threshold.
TMR
1V/DIV
HGATE
5V/DIV
FAULT
10V/DIV
ILOAD
10A/DIV
100ms/DIV
422712 F06
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