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| 型号： | LTC4230CGN#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/36页 |
| 文件大小： | 384K |
| 描述： | IC CONTRLLR HOT SWAP TRPL 20SSOP |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 1.7 V ~ 16.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 带卷 (TR) |
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9
LTC4230
4230f
PI FU CTIO S
U
U
GATE 1 (Pin 8): The output signal at this pin is the high side
gate drive for Channel 1s external N-channel FET pass
transistor. An internal charge pump produces a 4.5V
(minimum) to 18V (maximum) gate drive voltage for
supplies in the range of 2.7V d V
CC1
d 16.5V, respectively.
As shown in the Block Diagram, each channels internal
charge pump is powered by V
CC1
and supplies a 10礎 gate
current and sufficient gate voltage drive to the external
FET. The internal charge pump produces a minimum 4.5V
gate voltage drive for V
CC1
< 4.75V. For V
CC1
> 4.75V, the
minimum gate voltage drive is 9V. For V
CC1
e 12V, the
minimum gate voltage drive is 7V which is set by an
internal zener diode clamp connected between the GATE 1
pin and GND.
RESET 1 (Pin 9): An open-drain N-channel device whose
source connects to GND (Pin 14). This pin pulls low if the
voltage at FB1 (Pin 10) falls below the FB1 threshold
(1.234V). During the start-up cycle, RESET 1 goes high
impedance at the end of the second timing cycle after FB1
goes above the FB1 threshold. This pin requires an exter-
nal pull-up resistor to V
OUT1
. If an undervoltage lockout
condition occurs, RESET 1 pulls low independently of FB1
to prevent false glitches.
FB1 (Pin 10): The FB1 (Feedback) pin is an input to the
FBCOMP1 comparator which monitors the V
CC1
output
supply voltage through an external resistor divider. If V
FB1
< 1.234V, RESET 1 pin pulls low. An internal glitch filter at
FBCOMP3s output prevents triggering a reset condition
due to negative voltage transients. If V
FB1
> 1.237V after
the second timing cycle, RESET 1 goes high.
FILTER (Pin 11): Overcurrent Fault Timing Pin and Over-
voltage Fault Set Pin. With a capacitor connected from this
pin to ground, the response time of all three SLOW COMP
comparators can be adjusted. Note that the response time
of the SLOW COMP comparators cannot be adjusted
individually.
TIMER (Pin 12): A capacitor connected from this pin to
GND sets the LTC4230s system timing. The LTC4230s
initial and second start-up timing cycles and its discharge
mode delay time are controlled by this capacitor.
FAULT (Pin 13): FAULT is a dual function (an input and an
output) internal to the LTC4230. Connected to this pin are
an analog comparator (COMP6) and an open-drain
N-channel FET. During normal operation, if COMP6 is
driven below 1.234V, all electronic circuit breakers trip
and each GATE pin pulls low. Referring to the Block
Diagram, FAULT incorporates an internal 2礎 current
source pull up. This allows the LTC4230 to begin a second
timing cycle (V
FAULT
> 1.284V) and start up properly. This
also allows the use of the FAULT pin as a status output.
Under normal operating conditions, the FAULT output is a
logic high. Two conditions cause an active low on FAULT:
1) the LTC4230s electronic circuit breakers trip because
of an output short circuit (V
OUTn
= 0V) or because of a fast
output overcurrent transient (FAST COMPn trips its circuit
breaker); or 2) V
FILTER
> 1.26V. The FAULT output is driven
to logic low and is latched logic low until the ON pin is
driven to logic low for 30祍 (the t
RESET
duration).
GND (Pin 14): Device Ground Connection. Connect this
pin to the systems analog ground plane.
ON (Pin 15): An active high signal used to enable or disable
LTC4230 operation. As shown in the LTC4230 Block
Diagram, COMP1s threshold is set at 1.234V and its
hysteresis is set at 80mV. If a logic high signal is applied
to the ON pin (V
ON
> 1.314V), the first timing cycle begins
if an overvoltage condition does not exist on any of the
GATEn pins (Pins 3, 8, and 18). If a logic low signal is
applied to the ON pin (V
ON
< 1.234V), each GATEn pin is
pulled low by an internal, dedicated 200礎 current sink.
The ON pin can also be used to reset all three electronic
circuit breakers. If the ON pin is cycled low for more than 1
t
RESETn(MAX)
period and then high following a circuit
breaker trip, all internal circuit breakers are reset and the
LTC4230 begins a new start-up cycle.
V
CC2
(Pin 16): Positive Supply Input for Channel 2. V
CC2
operates from 2.375V to 16.5V and its supply current,
I
CC2
, is typically 75礎. The master UVLO circuit disables
all three GATEn outputs of the LTC4230 until the voltage
at V
CC2
exceeds 2.15V.
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| LTC4230IGN | 功能描述:IC CONTRLLR HOT SWAP TRPL 20SSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF) |
| LTC4230IGN#PBF | 功能描述:IC CONTRLLR HOT SWAP TRPL 20SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF) |
| LTC4230IGN#TR | 功能描述:IC CONTRLLR HOT SWAP TRPL 20SSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF) |
| LTC4230IGN#TRPBF | 功能描述:IC CONTRLLR HOT SWAP TRPL 20SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF) |
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