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| 型号： | LTC4230IGN#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 14/36页 |
| 文件大小： | 384K |
| 描述： | IC CONTRLLR HOT SWAP TRPL 20SSOP |
| 标准包装： | 55 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 1.7 V ~ 16.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 管件 |
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14
LTC4230
4230f
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
The LTC4230s power-on reset circuit initializes the start-
up condition and ensures the chip is in the proper state if
the input supply voltages are too low. If any one of the
input supply voltages falls below its corresponding UVLO
lower threshold (e.g., V
CC1
< 2.25V, V
CC2
< 2.105V or V
CC3
< 1.155V), the LTC4230 enters UVLO mode and all three
GATEn pins are each pulled low by internal 200礎 current
sinks. Since the LTC4230s UVLO circuits have hysteresis,
the device restarts when all three supply voltages rise
above their corresponding UVLO high threshold (e.g.,
V
CC1
> 2.35V, V
CC2
> 2.15V and V
CC3
> 1.19V) and the ON
pin goes high.
In addition, users can utilize the ON comparator (COMP1)
or the FAULT comparator (COMP6) to effectively program
a higher undervoltage lockout level. If the FAULT com-
parator is used for this purpose, the system will wait for
the input voltage to increase above the level set by the user
before starting the second timing cycle. Also, if the input
voltage drops below the set level in normal operating
mode, the user must cycle the ON pin or V
CC1
to restart the
system.
GLITCH FILTER FOR RESETn
Each LTC4230 feedback comparator has a glitch filter to
prevent RESETn from generating a system reset if there
are transients on the FBn pin. The relationship between
glitch filter time and the feedback transient voltage is
shown in Figure 3.
SYSTEM TIMING
System timing for the LTC4230 is generated in the equiva-
lent circuit shown in Figure 4. If the LTC4230s internal
timing circuit is off, an internal N-channel FET connects
the TIMER pin to GND. If the timing circuit is enabled, an
internal 20礎 current source is then connected to the
TIMER pin to charge C
TIMER
at a rate given by Equation 1:
C
Charge -Up Rate
TIMER
=
?/DIV>
20 A
C
TIMER
(1)
When the TIMER pin voltage reaches TMRHIs threshold
of 1.234V, the TIMER pin is reset to GND. Equation 2 gives
an expression for the timer period:
V
C
A
TIMER
TIMER
= 1 234
20
.
"
(2)
As a design aid, the LTC4230s timer period as a function
of the C
TIMER
using standard values from 0.1礔 to 10礔 is
shown in Table 1.
FEEDBACK TRANSIENT (mV)
0
150
200
250
160
4211 F03
100
50
0
40
80
120
20
180
60
100
140
200
T
A
= 25癈
Figure 3. FB Comparator Glitch Filter Time
vs Feedback Transient Voltage
+
0.3V
20礎
t
TIMER
LTC4230*
V
CC1
V
REF
1.234V
TMRLO
LOGIC
TMRHI
TIMER
C
TIMER
M6
NORMAL
4230 F04
*ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 4. LTC4230 System Timing Block Diagram
APPLICATIO S I FOR ATIO
U
U
U
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