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| 型号： | LTC4230IGN#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 18/36页 |
| 文件大小： | 384K |
| 描述： | IC CONTRLLR HOT SWAP TRPL 20SSOP |
| 标准包装： | 55 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 1.7 V ~ 16.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 管件 |
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18
LTC4230
4230f
USING AN EXTERNAL GATE CAPACITOR
The LTC4230 automatically limits the inrush current in one
of two ways: by controlling the GATEn pin voltage slew rate
or by actively limiting the inrush current. The LTC4230
uses GATEn voltage slew rate limiting when C
LOADn
is
small and/or the inrush current limit is set high. If GATEn
voltage slew rate control is preferred with large C
LOADn
, an
external capacitor (C
GX
) can be used from GATEn to ground,
as shown in Figure 7. According to Equation 3, adding C
GX
slows the GATEn voltage slew rate at the expense of slower
system turn-on and turn-off time. Should this technique
be used, values for C
GX
less than 150nF are recommended.
ELECTRONIC CIRCUIT BREAKER
The LTC4230 features an electronic circuit breaker func-
tion. It disconnects loads from power supplies when
shorts or excessive load current conditions occur on any
of the supplies and generates a FAULT signal. If a circuit
breaker trips, its GATEn pin is immediately pulled to
ground, the external N-channel MOSFET is quickly turned
OFF and FAULT is latched low.
The circuit breaker trips whenever the voltage across the
sense resistor exceeds two different levels, each level set
by the LTC4230s SLOW COMPn and FAST COMPn (see
Block Diagram). The SLOW COMPn trips the circuit
breaker if the voltage across the SENSEn resistor
(V
CCn
V
SENSEn
= V
CB
) is greater than 50mV for 10祍.
There may be applications where this comparators re-
sponse time is not long enough, for example, because of
excessive supply voltage noise. To adjust the response
time of the SLOW COMPn, a capacitor is used at the
LTC4230s FILTER pin (see section on Adjusting SLOW
COMPns Response Time). The FAST COMPn trips the
circuit breaker to protect against fast load overcurrents if
the transient voltage across the sense resistor is greater
than 150mV for 500ns. The response time of the LTC4230s
FAST COMPn is fixed.
The timing diagram of Figure 6 illustrates when the
LTC4230s electronic circuit breaker is armed. After the
first timing cycle, the LTC4230s FAST COMPn is armed
at Time Point 5. Arming FAST COMPn at Time Point 5
ensures that the system is protected against a short-
circuit condition during the second timing cycle after
C
LOADn
has been fully charged. At Time Point 8, SLOW
COMPn is armed when the internal control loop is disen-
gaged.
The timing diagrams in Figures 8 and 9 illustrate the opera-
tion of the LTC4230 when the load current conditions exceed
the thresholds of the FAST COMPn (V
CB(FAST)
> 150mV)
and SLOW COMPn (V
CB(SLOW)
> 50mV), respectively.
4
3
2
1
M1
Si4410DY
R
SENSE
0.007&
C
GX
*
C
LOAD
4230 F07
+
V
CCn
SENSEn
LTC4230**
GATEn
FBn
R1
36k
V
OUT
5V
5A
V
IN
5V
R2
15k
*
**
VALUES d150nF SUGGESTED
ADDITIONAL DETAILS OMITTED
FOR CLARITY
=
dV
GATEn
dt
V
GATE
SLEW RATE CONTROL
10礎
C
GATE
+ C
GX
(
)
Figure 7. Using an External Capacitor at GATE for
GATE Voltage Slew Rate Control and Large C
LOAD
An external gate capacitor may also be useful to decrease
or eliminate current spikes through the MOSFET when
power is first applied. At power-up, the instantaneous in-
put voltage step attempts to pull the MOSFET gate up
through the MOSFETs drain-to-gate capacitance. If the
MOSFETs C
ISS
is small, the gate can be pulled up high
enough to turn on the MOSFET, thereby allowing a current
spike to the output. This event occurs during the time that
the LTC4230 is coming out of UVLO and getting its intel-
ligence to hold the GATE pin low. An external capacitor
attenuates the voltage to which the GATE is pulled up and
eliminates the current spike. The value required is depen-
dent on the MOSFET capacitance specifications. In typical
applications, this capacitor is not required.
APPLICATIO S I FOR ATIO
U
U
U
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