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参数资料
| 型号： | LTC4232CDHC#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/16页 |
| 文件大小： | 242K |
| 描述： | IC CTLR HOT SWAP 5A 16-DFN |
| 标准包装： | 73 |
| 类型： | 热交换开关 |
| 应用： | 服务器，储存，通信，嵌入式，消费品 |
| 内部开关： | 是 |
| 电流限制： | 可调 |
| 电源电压： | 2.9 V ~ 15 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFDFN 裸露焊盘 |
| 供应商设备封装： | 16-DFN（5x3） |
| 包装： | 管件 |
LTC4232
9
4232fa
applicaTions inForMaTion
This gate slope is designed to charge up a 1000礔 capaci-
tor to 12V in 40ms, with an inrush current of 300mA. This
allows the inrush current to stay under the current limit
threshold (1.5A) for capacitors less than 1000礔. Included
in the Typical Performance Characteristics section is a
graph of the Safe Operating Area for the MOSFET. It is
evident from this graph that the power dissipation at 12V,
300mA for 40ms is in the safe region.
Adding a capacitor and a 1k series resistor from GATE to
ground will lower the inrush current below the default value
set by the INRUSH circuit. The GATE is charged with an
24礎 current source (when INRUSH circuit is not driving
the GATE). The voltage at the GATE pin rises with a slope
equal to 24礎/C
GATE
and the supply inrush current is set at:
I
INRUSH
=
C
L
C
GATE
" 24礎
When the GATE voltage reaches the MOSFET threshold
voltage, the switch begins to turn on and the OUT volt-
age follows the GATE voltage as it increases. Once OUT
reaches V
DD
, the GATE will ramp up until clamped by the
6.15V Zener between GATE and OUT.
As the OUT voltage rises, so will the FB pin which is moni-
toring it. Once the FB pin crosses its 1.235V threshold
and the GATE to OUT voltage exceeds 4.2V, the PG pin
will cease to pull low and indicate that the power is good.
Parasitic MOSFET Oscillation
When the N-channel MOSFET ramps up the output during
power-up it operates as a source follower. The source
follower configuration may self-oscillate in the range of
25kHz to 300kHz when the load capacitance is less than
Figure 2. Supply Turn-On
Figure 1. 2A, 12V Card Resident Application
The typical LTC4232 application is in a high availability
system that uses a positive voltage supply to distribute
power to individual cards. A complete application circuit
is shown in Figure 1. External component selection is
discussed in detail in the following sections.
ADC
R1
226k
C1
0.1礔
R2
20k
12V
4232 F01
C
T
0.1礔
C
L
330礔
V
OUT
12V
2A
V
DD
UV
OUT
FB
PG
GND
I
MON
R
SET
20k
R
MON
20k
I
SET
C
GATE
0.1礔
R
GATE
1k
GATE
LTC4232
OV
INTV
CC
TIMER
FLT
+
R3
140k
R4
20k
R7
10k
R6
20k
R5
150k
t1
t2
SLOPE = 0.3V/ms
GATE
OUT
V
DD
+ 6.15
V
DD
4232 F02
Turn-On Sequence
Several conditions must be present before the internal
pass MOSFET can be turned on. First the supply V
DD
must
exceed its undervoltage lockout level. Next the internally
generated supply INTV
CC
must cross its 2.65V undervolt-
age threshold. This generates a 25祍 power-on-reset pulse
which clears the fault register and initializes internal latches.
After the power-on-reset pulse, the LTC4232 will go
through the following sequence. First, the UV and OV pins
must indicate that the input voltage is within the accept-
able range. All of these conditions must be satisfied for
the duration of 100ms to ensure that any contact bounce
during the insertion has ended.
The MOSFET is turned on by charging up the GATE with
a charge pump generated current source whose value is
adjusted by shunting a portion of the pull-up current to
ground. The charging current is controlled by the INRUSH
circuit that maintains a constant slope of GATE voltage
versus time (Figure 2). The voltage at the GATE pin rises
with a slope of 0.3V/ms and the supply inrush current is
set at:
I
INRUSH
= C
L
" (0.3V/ms)
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