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| 型号： | LTC4244IGN#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 19/28页 |
| 文件大小： | 337K |
| 描述： | IC CTRLR HOTSWAP PCI 20-SSOP |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | CompactPCI? |
| 内部开关： | 无 |
| 电源电压： | 3.3V，5V，±12V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 带卷 (TR) |
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19
LTC4244/LTC4244-1
42441f
APPLICATIO S I FOR ATIO
U
U
U
BD_SEL# voltage drops below 4.4V thus causing the bus
switch OE to be pulled high by Q2.
The CompactPCI specification assumes that there is a
diode to 3.3V on the circuit that is driving the BD_SEL# pin.
The 1.2k resistor pull-up to 5V
IN
on the plug-in card will be
clamped by the diode to 3.3V. If the BD_SEL# pin is being
driven high, the actual voltage on the pin will be approxi-
mately 3.9V. This is still above the high TTL threshold of
the LTC4244 OFF/ON pin, but low enough for Q2 to disable
the bus switches and thus disconnect the 10k precharge
resistors from the I/O lines. Since the power to the bus
switch is derived from a front-end power plane, a 100&
resistor should be placed in series with the power supply
of the bus switch.
When the plug-in card is removed from the connector, the
BD_SEL# connection is broken first, and the BD_SEL#
voltage pulls up to 5V
IN
. This causes Q2 to turn off, which
re-enables the bus switch, and the precharge resistors are
again connected to the LTC4244 PRECHARGE pin for the
remainder of the extraction process.
TIMER/Auxiliary V
CC
Once the TIMER pin voltage has ramped to within 1.6V of
12V
IN
, the auxiliary V
CC
function is enabled. In the event
the 12V
IN
supply voltage collapses, the LTC4244 will
continue to draw power from the charge stored on the
TIMER pin capacitor until the internal V
CC
node drops
below its undervoltage lockout threshold or the 12V
IN
supply voltage recovers, whichever happens first.
Other CompactPCI Applications
The LTC4244-1 is designed for CompactPCI designs
where the 12V supply is not being used on the plug-in
board. The V
EEOUT
power good comparator, V
EEIN
UVL,
and V
EE
circuit breaker functions are disabled. The V
EEIN
pin should be connected to GND and the V
EEOUT
pin left
floating if a 12V output is not needed.
If no 3.3V supply input is required, Figure 10 illustrates
how the LTC4244 should be configured: 3.3V
SENSE
and
3.3V
IN
are connected to 5V
IN
and 3.3V
OUT
is connected to
5V
OUT
.
For applications where the BD_SEL# connector pin is
typically connected to ground on the backplane, the circuit
in Figure 11 allows the LTC4244 to be reset simply by
pressing a pushbutton switch on the CPCI plug in board.
This arrangement eliminates the requirement to extract
and reinsert the CPCI board in order to reset the LTC4244s
circuit breaker.
C1
0.33礔
5V
IN
13
17
16
18
3
15
14
8
R4
10&
5V
OUT
4244 F10
R5
1k
R2
0.007&
Q2
IRF7457
Z4
Z4: SMAJ5.0A
*ADDITIONAL PINS OMITTED FOR CLARITY
PCB EDGE
BACKPLANE
CONNECTOR
BACKPLANE
CONNECTOR
5V
LONG 5V
GROUND
GND
5V
IN
5V
SENSE
3.3V
OUT
3.3V
IN
LTC4244*
5V
OUT
3.3V
SENSE
GATE
Figure 10. No 3.3V Supply Application Circuit
8
1.2k
PUSHBUTTON
SWITICH
100&
0.25W
V(I/O)
1k
GROUND
5
BD_SEL#
4244 F11
*ADDITIONAL PINS OMITTED FOR CLARITY
PCB EDGE
BACKPLANE
CONNECTOR
BACKPLANE
CONNECTOR
GND
LTC4244*
OFF/ON
Figure 11. BD_SEL# Pushbutton Toggle Switch
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