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参数资料
| 型号： | LTC4245IUHF#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/36页 |
| 文件大小： | 431K |
| 描述： | IC CNTRLR HOT SWAP 38-QFN |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | CompactPCI? |
| 内部开关： | 无 |
| 电源电压： | 3.3V，5V，12V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 供应商设备封装： | 38-QFN（5x7） |
| 包装： | 带卷 (TR) |
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LTC4245
16
4245fa
When a switch is to be turned on, an internal 100糀 cur-
rent source is connected to the TIMER pin and a 20糀
current to SS pin. The gate of each ramping supplys pass
transistor is servoed by an internal ampli er, so the supply
current never exceeds an internal current limit. This internal
current limit starts off with a negative value, which makes
the ampli er pull the gate low. The voltage ramp on the
SS pin is converted to a current limit rising linearly with
time. The ampli er releases the gate as the current limit
crosses zero. An internal current source starts charging
up the gate. When the gate voltage reaches the MOSFET
threshold voltage, the switch begins to turn on. The
ampli er once again starts modulating the gate pull-up
current so that the sense resistor voltage drop follows the
internally set current limit. The rate of rise of the inrush
current is given by:
dI
dt
G
R
dV
dt
INRUSH
SS
SENSE
SS
=
"
(1)
dV
dt
I
C
SS SS
SS
=
(2)
G
SS
is the ratio of the change in current limit to the change
in SS pin voltage. The rising current limit will stop at a
level depending on the foldback circuit. The foldback circuit
monitors the outputs of all supplies which are ramping.
In the worst case, a supply output could be shorted to
ground. In this case the foldback circuit reduces the cur-
rent limit to 30% of the maximum as shown in the Typical
Performance Curves. To set an inrush current lower than
the foldback level, a series R-C network can be connected
between the gate pin and ground (V
EEOUT
for 12V supply)
(Figure 3). This allows charging the output load beyond
the time dictated by the TIMER capacitor. When the rising
internal current limit exceeds the dV/dt set inrush current,
the current limit ampli er goes open loop. If any ramping
supplys ampli er is open loop the SS pin current drops
to 2糀 from 20糀, thus slowing the current limit rise.
This would affect the other supplies ramp-up in case of
simultaneous turn-on. A 100k?resistance ensures that
the capacitor charge is decoupled during a fast gate turn-
off. The capacitor value is determined by:
C
I
I
C
GATE
GATE UP
INRUSH
LOAD
=
( )
"
(3)
Meanwhile the TIMER pin ramps up to 2.56V, when it is
reset to ground. Current limit faults on the ramping supplies
are ignored during this time period. The start-up timing
cycle ends when the TIMER pin falls below 0.23V. The SS
pin is reset, the circuit breaker for the supply is armed and
its current limit raised to 3x the circuit breaker threshold.
In a sequenced turn-on the part will start another TIMER
and SS cycle to ramp up the next supply. If supplies are
being turned on through the serial bus, it will wait for the
next turn-on command.
Once all supplies have been turned on and all their outputs
are within tolerance, HEALTHY# will pull low and LO-
CAL_PCI_RST#, which was low, will now follow PCI_RST#.
The TIMER pin is now pulled up by a 10糀 current source
while SS pin remains in reset. When TIMER reaches 2.56V,
it is reset to ground. As it crosses 0.23V the PGI pin is
sampled. If it is low then all switches are turned off.
APPLICATIO S I FOR ATIO
U
U
U
TIME 50ms/DIV
SS
2.5V/DIV
TIMER
2.5V/DIV
4245 F02
12V
OUT
, 5V
OUT
3V
OUT
, V
EEOUT
, 10V/DIV
BD_SEL#
5V/DIV
HEALTHY#
5V/DIV
LOCAL_PCI_RST#
5V/DIV
Figure 2. Normal Turn-On Waveform
Figure 3. C
GATE
for dV/dt Limited Inrush Current
34
18
17
4245 F03
R26
100k
R6
10&
R8
10&
Q2, Si7880DP
V
EEGATE
5V
GATE
C
GATE(5V)
LTC4245G*
V
EEOUT
Q4, Si4872
R27
100k
C
GATE(VEE)
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
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