参数资料
型号: LTC4245IUHF#TRPBF
厂商: Linear Technology
文件页数: 5/36页
文件大小: 431K
描述: IC CNTRLR HOT SWAP 38-QFN
标准包装: 2,500
类型: 热交换控制器
应用: CompactPCI?
内部开关:
电源电压: 3.3V,5V,12V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 38-WFQFN 裸露焊盘
供应商设备封装: 38-QFN(5x7)
包装: 带卷 (TR)
LTC4245
5
4245fa
 
The ?/SPAN> denotes the speci cations which apply over the full operating temperature
range, otherwise speci cations are at T
A
 = 25癈. V
12VIN
 = 12V, V
5VIN
 = 5V, V
3VIN
 = 3.3V, V
VEEIN
 = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ADC
RES
Resolution (No Missing Codes)
(Note 7)
?/DIV>
8
Bits
V
FS
Full-Scale Voltage (V
FS
 = 255LSB)
    12V
IN
, 12V
OUT
    12V
IN
  12V
SENSE
,
 
V
EESENSE
  V
EEIN
    5V
IN
, 5V
OUT
    5V
IN
  5V
SENSE
, 3V
IN
  3V
SENSE
    3V
IN
, 3V
OUT
    V
EEIN
, V
EEOUT
    GPIO
(Note 6)
V
CFG
 = 0V, Open
V
CFG
 = V
CC
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
13.744
62.47
5.5
3.75
31.24
3.75
13.744
2.5
14.025
63.75
5.61
3.825
31.875
3.825
14.025
2.55
14.306
65.03
5.72
3.9
32.51
3.9
14.306
2.6
V
mV
V
V
mV
V
V
V
INL
Integral Nonlinearity
SENSE
 (Note 8)
Other 9 Channels
?/DIV>
?/DIV>
?.5
?.2
?
?.25
LSB
LSB
OE
Offset Error
SENSE
 (Note 6)
V
EEIN
, V
EEOUT
Other 7 Channels
?/DIV>
?/DIV>
?/DIV>
?.5
?.5
?.3
?.5
?.25
?
LSB
LSB
LSB
FSE
Full-Scale Error
?/DIV>
?
LSB
TUE
Total Unadjusted Error
?/DIV>
?
LSB
t
ADC
Conversion Time
All 13 Channels Once
SENSE
, V
EEIN
, V
EEOUT
Other 7 Channels
665
70
35
ms
ms
ms
Delays
t
D
Turn-On Delay
?/DIV>
60
100
150
ms
t
PLH(GATE)
Input High (ON) to Gates High Delay
SS Open
?/DIV>
15
30
t
PHL(GATE)
Input High (BD_SEL#), Input Low (ON)
to Gates Low Propagation Delay
C
GATE
 = 1pF
?/DIV>
0.3
1
t
PHL(UVL)
Supply Low to Gates Low Delay
12V
IN
, 5V
IN
, 3V
IN
, C
GATE
 = 1pF
V
EEIN
, C
VEEGATE
 = 1pF
?/DIV>
?/DIV>
2.1
3.3
3.5
5.5
4.9
7.7
t
CB
Circuit Breaker Filter Delay Time
?/DIV>
16
22
28
t
ACL
Active Current Limit Delay
12VSENSE
 = 300mV, C
12VGATE
 = 10nF
5VSENSE
 = 150mV, C
5VGATE
 = 10nF
3VSENSE
 = 150mV, C
3VGATE
 = 10nF
VEESENSE
 = 300mV, C
VEEGATE
 = 10nF
?/DIV>
?/DIV>
?/DIV>
?/DIV>
0.9
0.85
0.7
2
2.3
2.1
1.8
5
t
PHL(PGI)
PGI Low to Gates Low
C
GATE
 = 1pF
?/DIV>
12
20
28
t
PHL(RST)
Output Low to LOCAL_PCI_RST# Low
12V
OUT
, 5V
OUT
, 3V
OUT
, V
PCI_RST#
 = 2V
V
EEOUT
, V
PCI_RST#
 = 2V
?/DIV>
?/DIV>
9
10.2
15
17
21
23.8
t
P(RST)
PCI_RST# to LOCAL_PCI_RST# Delay
?/DIV>
60
200
ns
I
2
C Interface Timing (Note 7)
f
SCL(MAX)
Maximum SCL Clock Frequency
Operates with f
SCL
 d f
SCL(MAX)
400
kHz
t
BUF(MIN)
Min. Bus Free Time Between Stop/Start
0.12
1.3
t
SU, STA(MIN)
Minimum Repeated Start Set-Up Time
10
600
ns
t
HD, STA(MIN)
Min. Hold Time After (Repeated) Start
140
600
ns
t
SU, STO(MIN)
Minimum Stop Condition Set-Up Time
10
600
ns
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