参数资料
型号: LTC4252A-2CMS#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 电源管理
英文描述: Negative Voltage Hot Swap Controllers; Package: MSOP; No of Pins: 10; Temperature Range: 0°C to +70°C
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10
封装: LEAD FREE, PLASTIC, MSOP-10
文件页数: 14/36页
文件大小: 394K
代理商: LTC4252A-2CMS#PBF
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
21
425212fb
APPLICATIO S I FOR ATIO
WU
U
Figure 7. Recommended Compensation
Capacitor CC vs MOSFET CISS
MOSFET CISS (pF)
0
COMPENSATION
CAPACITANCE
C
(nF)
60
50
40
30
20
10
0
2000
4000
4252-1/2 F07
6000
8000
NTY100N10
IRF3710
IRF540S
IRF530S
IRF740
Figure 8. Making PCB Connections to the Sense Resistor
W
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO –48V BACKPLANE
SENSE RESISTOR
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
TO
SENSE
TO
VEE
4252-1/2 F08
As seen in Figure 6 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramati-
cally owing to series inductance. If this voltage avalanches
the MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4252’s
VEE and SENSE pins are strongly recommended. The
drawing in Figure 8 illustrates the correct way of making
connections between the LTC4252 and the sense resistor.
PCB layout should be balanced and symmetrical to mini-
mize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
TIMING WAVEFORMS
System Power-Up
Figure 9 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV,
VOUT and DRAIN. VIN and PWRGD follow at a slower rate
as set by the VIN bypass capacitor. At time point 2, VIN
exceeds VLKO and the internal logic checks for UV > VUVHI,
OV < VOVLO, GATE < VGATEL, SENSE < VCB, SS < 20 VOS
and TIMER < VTMRL. If all conditions are met, an initial
timing cycle starts and the TIMER capacitor is charged by
a 5.8
A current source pull-up. At time point 3, TIMER
reaches the VTMRH threshold and the initial timing cycle
terminates. The TIMER capacitor is quickly discharged. At
time point 4, the VTMRL threshold is reached and the
conditions of GATE < VGATEL, SENSE < VCB and
SS<20VOS must be satisfied before a GATE ramp-up
cycle begins. SS ramps up as dictated by RSS CSS (as in
Equation 6); GATE is held low by the analog current limit
(ACL) amplifier until SS crosses 20 VOS. Upon releasing
GATE, 58
A sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFET’s threshold, current begins flowing into the
load capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
VACL(t) (Equation 7) and soft-start limits the slew rate of
the load current. If the SENSE voltage (VSENSE – VEE)
reaches the VCB threshold at time point 7, the circuit
breaker TIMER activates. The TIMER capacitor, CT, is
charged by a (230
A+8IDRN)currentpull-up.Astheload
capacitor nears full charge, load current begins to decline.
相关PDF资料
PDF描述
LTC4252A-2CMS#TRPBF Negative Voltage Hot Swap Controllers; Package: MSOP; No of Pins: 10; Temperature Range: 0&deg;C to +70&deg;C
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