参数资料
型号: LTC4252A-2CMS#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 电源管理
英文描述: Negative Voltage Hot Swap Controllers; Package: MSOP; No of Pins: 10; Temperature Range: 0°C to +70°C
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10
封装: LEAD FREE, PLASTIC, MSOP-10
文件页数: 36/36页
文件大小: 394K
代理商: LTC4252A-2CMS#PBF
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
9
425212fb
TYPICAL PERFOR A CE CHARACTERISTICS
UW
tSS vs Temperature
VIN (Pin 1/Pin 1): Positive Supply Input. Connect this pin
to the positive side of the supply through a dropping
resistor. A shunt regulator clamps VIN at 13V. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the VIN pin is greater than VLKO, overriding UV and OV. If
UV is high, OV is low and VIN comes out of UVLO, TIMER
starts an initial timing cycle before initiating a GATE ramp-
up. If VIN drops below approximately 8.2V, GATE pulls low
immediately.
PWRGD (Pin 2/Not Available): Power Good Status Out-
put (MS only). At start-up, PWRGD latches low if DRAIN
is below 2.385V and GATE is within 2.8V of VIN. PWRGD
status is reset by UV, VIN (UVLO) or a circuit breaker fault
timeout. This pin is internally pulled high by a 58
Acurrent
source.
SS (Pin 3/Pin 2): Soft-Start Pin. This pin is used to ramp
inrush current during start up, thereby effecting control
over di/dt. A 20x attenuated version of the SS pin voltage
is presented to the current limit amplifier. This attenuated
voltage limits the MOSFET’s drain current through the
sense resistor during the soft-start current limiting. At the
beginning of a start-up cycle, the SS capacitor (CSS) is
ramped by a 22
A (28A for the LTC4252A) current
source. The GATE pin is held low until SS exceeds 20 VOS
= 0.2V. SS is internally shunted by a 100k resistor (RSS)
which limits the SS pin voltage to 2.2V(50k resistor and
1.4V for the LTC4252A). This corresponds to an analog
current limit SENSE voltage of 100mV (60mV for the
LTC4252A). If the SS capacitor is omitted, the SS pin
ramps up in about 180
s. The SS pin is pulled low under
any of the following conditions: in UVLO, in an undervolt-
age condition, in an overvoltage condition, during the
initial timing cycle or when the circuit breaker fault times
out.
SENSE (Pin 4/Pin 3): Circuit Breaker/Current Limit Sense
Pin. Load current is monitored by a sense resistor RS
connected between SENSE and VEE, and controlled in
three steps. If SENSE exceeds VCB (50mV), the circuit
breaker comparator activates a (230
A + 8 IDRN) TIMER
pull-up current. If SENSE exceeds VACL, the analog current
limit amplifier pulls GATE down to regulate the MOSFET
current at VACL/RS. In the event of a catastrophic short-
circuit, SENSE may overshoot. If SENSE reaches VFCL
(200mV), the fast current limit comparator pulls GATE low
with a strong pull-down. To disable the circuit breaker and
current limit functions, connect SENSE to VEE.
PI FU CTIO S
UU
U
IPGH vs Temperature
tPLLUG and tPHLOG
vs Temperature
TEMPERATURE
°(C)
–55 –35 –15
5
25
45
65
85 105 125
I PGH
(
A)
4252-1/2 G38
62
61
60
59
58
57
56
55
VPWRGD = 0V
(MS ONLY)
TEMPERATURE (
°C)
–55 –35 –15
5
25
45
65
85 105 125
t SS
(
s)
4252-1/2 G27
220
210
200
190
180
170
160
150
SS PIN FLOATING,
VSS RAMPS FROM 0.2V TO 2V
TEMPERATURE (
°C)
–55
DELAY
(
s)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–15
25
45
125
4252-1/2 G24
–35
5
65
85 105
tPLLUG
tPHLOG
(MS/MS8)
相关PDF资料
PDF描述
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