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参数资料
| 型号： | LTC4253ACGN#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/34页 |
| 文件大小： | 383K |
| 描述： | IC HOT SWAP CONTRLR -48V 16-SSOP |
| 标准包装： | 100 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 8.2 V ~ 14.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 管件 |
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LTC4253/LTC4253A
8
425353aff
For more information www.linear.com/4253
TYPICAL PERFORMANCE CHARACTERISTICS
I
PGH
vs Temperature
t
SS
vs Temperature
t
SQ
vs Temperature
TEMPERATURE (癈)
55 35 15 5 25 45 65 85 105 125
4253 G28
60
58
56
54
52
50
48
46
44
42
40
I
IN
= 2mA
V
PWRGD
= 0V
TEMPERATURE (癈)
55 35 15 5 25 45 65 85 105 125
4253 G29
300
290
280
270
260
250
240
230
220
210
200
I
IN
= 2mA
SS PIN FLOATING
V
SS
RAMPS FROM 0.2V TO 2V
TEMPERATURE (癈)
55 35 15 5 25 45 65 85 105 125
4253 G30
500
450
400
350
300
250
200
150
100
50
0
I
IN
= 2mA
V
SQTMR
RAMPS FROM 0.5V TO 3.5V
EN2 (Pin 1): Power Good Status Output Two Enable. This
is a TTL compatible input that is used to control PWRGD2
and PWRGD3 outputs. When EN2 is driven low, both
PWRGD2 and PWRGD3 will go high. When EN2 is driven
high, PWRGD2 will go low provided PWRGD1 has been
active for more than one power good sequence delay
(t
SQT
) provided by the sequencing timer. EN2 can be used
to control the power good sequence. This pin is internally
pulled low by a 120礎 current source.
PWRGD2 (Pin 2): Power Good Status Output Two. Power
good sequence starts with PWRGD1 latching active low.
PWRGD2 will latch active low after EN2 goes high and
after one power good sequence delay t
SQT
provided by
the sequencing timer from the time PWRGD1 goes low,
whichever comes later. PWRGD2 is reset by PWRGD1
going high or EN2 going low. This pin is internally pulled
high by a 50礎 current source.
PWRGD1 (Pin 3): Power Good Status Output One. At start-
up, PWRGD1 latches active low and starts the power good
sequence when the DRAIN pin is below 2.39V and GATE
is within 2.8V of V
IN
. PWRGD1 status is reset by UV , V
IN
(UVLO), RESET going high or circuit breaker fault time-out.
This pin is internally pulled high by a 50礎 current source.
V
IN
(Pin 4): Positive Supply Input. Connect this pin to the
positive side of the supply through a dropping resistor. A
shunt regulator clamps V
IN
at 13V above V
EE
. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the V
IN
pin is greater than V
LKO
, overriding UV and OV . If
UV is high, OV is low and V
IN
comes out of UVLO, TIMER
starts an initial timing cycle before initiating GATE ramp
up. If V
IN
drops below approximately 8.2V (8.5V for the
LTC4253A), GATE pulls low immediately.
RESET (Pin 5): Circuit Breaker Reset Pin. This is an asyn-
chronous TTL compatible input. RESET going high will pull
GATE, SS, TIMER, SQTIMER low
and the PWRGD outputs
high. The RESET pulse must be wide enough to discharge
any voltage on the TIMER pin below V
TMRL
. After the reset
of a latched fault, the chip waits for the interlock conditions
before recovering as described in Interlock Conditions in
the Operation section.
SS (Pin 6): Soft-Start Pin. This pin is used to ramp inrush
current during start up, thereby effecting control over di/dt.
A 20X attenuated version of the SS pin voltage is presented
to the current limit amplifier. This attenuated voltage limits
the MOSFETs drain current through the sense resistor
during the soft-start current limiting. At the beginning of
PIN FUNCTIONS
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