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参数资料
| 型号： | LTC4253ACGN#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | -48V Hot Swap Controller with Sequencer; Package: SSOP; No of Pins: 16; Temperature Range: 0°C to +70°C |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封装： | 0.150 INCH, LEAD FREE, PLASTIC, SSOP-16 |
| 文件页数： | 21/34页 |
| 文件大小： | 369K |
| 代理商： | LTC4253ACGN#PBF |
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LTC4253/LTC4253A
28
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applicaTions inForMaTion
Resetting a Fault Latch
A latched circuit breaker fault of the LTC4253/LTC4253A
has the benefit of a long cooling time. The latched fault can
be reset by pulsing the RESET pin high until the TIMER pin
is pulled below VTMRL(1V) as shown in Figure 13b. After
the RESET pulse, SS and GATE ramp up without an initial
timingcycleprovidedtheinterlockconditionsaresatisfied.
Alternative methods of reset include using an external
switch to pulse the UV pin below VUVLO (VUV – VUVHST
for the LTC4253A) or the VIN pin below (VLKO – VLKH).
Pulling the TIMER pin below VTMRL and the SS pin to 0V
then simultaneously releasing them also achieves a reset.
An initial timing cycle is generated for reset by pulsing the
UV pin or VIN pin, while no initial timing cycle is generated
for reset by pulsing of the TIMER and SS pins.
Using Reset as an ON/OFF Switch
The asynchronous RESET pin can be used as an ON/OFF
function to cut off supply to the external power modules
or loads controlled by the LTC4253/LTC4253A. Pulling
RESET high will pull GATE, SS, TIMER and SQTIMER
low and the PWRGD signal high. The supply is fully cut
off if the RESET pulse is maintained wide enough to fully
discharge the GATE and SS pins. As long as RESET is
high, GATE, SS, TIMER and SQTIMER are strapped to VEE
and the supply is cut off. When RESET is released, if the
LTC4253/LTC4253A are in UVLO, UV, OV or VSENSE > VCB,
turn-on is delayed until the interlock conditions are met
before recovering as described in the Operation, Interlock
Conditions section. If not, the GATE pin will ramp up in a
soft start cycle without going through an initial cycle as
in Figure 13c.
Analog Current Limit and Fast Current Limit
InFigure14a,whenSENSEexceedsVACL,GATEisregulated
by the analog current limit amplifier loop. When SENSE
dropsbelowVACL,GATEisallowedtopullup.InFigure14b,
whenaseverefaultoccurs,SENSEexceedsVFCLandGATE
immediately pulls down until the analog current amplifier
establishescontrol.IftheseverefaultcausesVOUTtoexceed
VDRNCL, the DRAIN pin is clamped at VDRNCL. IDRN flows
into the DRAIN pin and is multiplied by8. This extra cur-
rent is added to the TIMER pull-up current of 200A. This
accelerated TIMER current of (200A+8IDRN) produces
a shorter circuit breaker fault delay. Careful selection of
CT, RD and MOSFET helps prevent SOA damage in a low
impedance fault condition.
Soft-Start
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 2.2V in about 300s (0V to 1.4V
in about 200s for the LTC4253A) at GATE start-up, as
shown in Figure 15a. If a soft-start capacitor, CSS, is con-
nected to this SS pin, the soft-start response is modified
from a linear ramp to an RC response (Equation6), as
shown in Figure 15b. This feature allows load current to
slowly ramp-up at GATE start-up. Soft-start is initiated at
time point 3 by a TIMER transition from VTMRH to VTMRL
(time points 1 and 2), by the OV pin falling below the VOVLO
(VOV – VOVHST for the LTC4253A) threshold after an OV
condition or by the RESET pin falling < 0.8V after a Reset
condition. When the SS pin is below 0.2V, the analog cur-
rent limit amplifier keeps GATE low. Above 0.2V, GATE is
released and 50A ramps up the compensation network
and GATE capacitance at time point 4. Meanwhile, the SS
pin voltage continues to ramp up. When GATE reaches
the MOSFET’s threshold, the MOSFET begins to conduct.
Due to the MOSFET’s high gm,theMOSFETcurrentquickly
reachesthesoft-startcontrolvalueofVACL(t)(Equation7).
Attimepoint6,theGATEvoltageiscontrolledbythecurrent
limit amplifier. The soft-start control voltage reaches the
circuit breaker voltage, VCB at time point7 and the circuit
breaker TIMER activates. As the load capacitor nears full
charge, load current begins to decline below VACL(t). The
current limit loop shuts off and GATE releases at time
point8. At time point9, SENSE voltage falls below VCB
and TIMER deactivates.
Large values of CSS can cause premature circuit breaker
time-outasVACL(t)maymarginallyexceedtheVCBpotential
during the circuit breaker delay. The load capacitor is un-
able to achieve full charge in one GATE start-up cycle. A
more serious side effect of a large CSS value is that SOA
duration may be exceeded during soft-start into a low
impedance load. A soft-start voltage below VCB will not
activate the circuit breaker TIMER.
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相关代理商/技术参数 |
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| LTC4253ACUF-ADJ#PBF | 制造商:Linear Technology 功能描述:Hot Swap Controller 1-CH 20-Pin QFN EP |
| LTC4253ACUF-ADJ#TRPBF | 制造商:Linear Technology 功能描述:Hot Swap Controller 1-CH 20-Pin QFN EP T/R |
| LTC4253AIGN#PBF | 功能描述:IC HOT SWAP CONTRLR -48V 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:100 系列:- 类型:热插拔开关 应用:通用 内部开关:是 电流限制:可调 电源电压:9 V ~ 13.2 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:10-WFDFN 裸露焊盘 供应商设备封装:10-TDFN-EP（3x3） 包装:管件 |
| LTC4253AIGN#TRPBF | 功能描述:IC HOT SWAP CONTRLR -48V 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:100 系列:- 类型:热插拔开关 应用:通用 内部开关:是 电流限制:可调 电源电压:9 V ~ 13.2 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:10-WFDFN 裸露焊盘 供应商设备封装:10-TDFN-EP（3x3） 包装:管件 |
| LTC4253AIGN-ADJ | 制造商:LINER 制造商全称:Linear Technology 功能描述:-48V Hot Swap Controller with Sequencer |
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