参数资料
型号: LTC4253ACGN#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 电源管理
英文描述: -48V Hot Swap Controller with Sequencer; Package: SSOP; No of Pins: 16; Temperature Range: 0°C to +70°C
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16
封装: 0.150 INCH, LEAD FREE, PLASTIC, SSOP-16
文件页数: 33/34页
文件大小: 369K
代理商: LTC4253ACGN#PBF
LTC4253/LTC4253A
8
425353afd
Typical perForMance characTerisTics
IPGH vs Temperature
tSS vs Temperature
tSQ vs Temperature
TEMPERATURE (°C)
–55 –35 –15 5
25 45 65 85 105 125
V PGH
(A)
4253 G28
60
58
56
54
52
50
48
46
44
42
40
IIN = 2mA
VPWRGD = 0V
TEMPERATURE (°C)
–55 –35 –15 5
25 45 65 85 105 125
t SS
(s)
4253 G29
300
290
280
270
260
250
240
230
220
210
200
IIN = 2mA
SS PIN FLOATING
VSS RAMPS FROM 0.2V TO 2V
TEMPERATURE (°C)
–55 –35 –15 5
25 45 65 85 105 125
t SQ
(s)
4253 G30
500
450
400
350
300
250
200
150
100
50
0
IIN = 2mA
VSQTMR RAMPS FROM 0.5V TO 3.5V
EN2 (Pin 1): Power Good Status Output Two Enable. This
is a TTL compatible input that is used to control PWRGD2
and PWRGD3 outputs. When EN2 is driven low, both
PWRGD2 and PWRGD3 will go high. When EN2 is driven
high, PWRGD2 will go low provided PWRGD1 has been
active for more than one power good sequence delay
(tSQT) provided by the sequencing timer. EN2 can be used
to control the power good sequence. This pin is internally
pulled low by a 120A current source.
PWRGD2 (Pin 2): Power Good Status Output Two. Power
good sequence starts with PWRGD1 latching active low.
PWRGD2 will latch active low after EN2 goes high and
after one power good sequence delay tSQT provided by
the sequencing timer from the time PWRGD1 goes low,
whichever comes later. PWRGD2 is reset by PWRGD1
going high or EN2 going low. This pin is internally pulled
high by a 50A current source.
PWRGD1(Pin3):PowerGoodStatusOutputOne.Atstart-
up, PWRGD1 latches active low and starts the power good
sequence when the DRAIN pin is below 2.39V and GATE
is within 2.8V of VIN. PWRGD1 status is reset by UV, VIN
(UVLO),RESETgoinghighorcircuitbreakerfaulttime-out.
This pin is internally pulled high by a 50A current source.
VIN (Pin 4): Positive Supply Input. Connect this pin to the
positive side of the supply through a dropping resistor. A
shunt regulator clamps VIN at 13V above VEE. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the VIN pin is greater than VLKO, overriding UV and OV. If
UV is high, OV is low and VIN comes out of UVLO, TIMER
starts an initial timing cycle before initiating GATE ramp
up. If VIN drops below approximately 8.2V (8.5V for the
LTC4253A), GATE pulls low immediately.
RESET (Pin 5): Circuit Breaker Reset Pin. This is an asyn-
chronousTTLcompatibleinput.RESETgoinghighwillpull
GATE, SS, TIMER, SQTIMER low and the PWRGD outputs
high. The RESET pulse must be wide enough to discharge
any voltage on the TIMER pin below VTMRL. After the reset
of a latched fault, the chip waits for the interlock conditions
before recovering as described in Interlock Conditions in
the Operation section.
SS (Pin 6): Soft-Start Pin. This pin is used to ramp inrush
currentduringstartup,therebyeffectingcontroloverdi/dt.
A20XattenuatedversionoftheSSpinvoltageispresented
to the current limit amplifier. This attenuated voltage limits
the MOSFET’s drain current through the sense resistor
during the soft-start current limiting. At the beginning of
pin FuncTions
相关PDF资料
PDF描述
LTC4253ACGN#TRPBF -48V Hot Swap Controller with Sequencer; Package: SSOP; No of Pins: 16; Temperature Range: 0°C to +70°C
LTC4253AIGN#PBF -48V Hot Swap Controller with Sequencer; Package: SSOP; No of Pins: 16; Temperature Range: -40°C to +85°C
LTC4253AIGN#TRPBF -48V Hot Swap Controller with Sequencer; Package: SSOP; No of Pins: 16; Temperature Range: -40°C to +85°C
LTC4253CGN#PBF -48V Hot Swap Controller with Sequencer; Package: SSOP; No of Pins: 16; Temperature Range: 0°C to +70°C
LTC4253CGN#TRPBF -48V Hot Swap Controller with Sequencer; Package: SSOP; No of Pins: 16; Temperature Range: 0°C to +70°C
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