参数资料
型号: LTC4261CUFD-2#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 电源管理
英文描述: Negative Voltage Hot Swap Controllers with ADC and I2C Monitoring; Package: QFN; No of Pins: 24; Temperature Range: 0°C to +70°C
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24
封装: 4 X 5 MM, LEAD FREE, PLASTIC, QFN-24
文件页数: 34/34页
文件大小: 357K
代理商: LTC4261CUFD-2#PBF
LTC4261/LTC4261-2
9
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PGI (Pin 1/Pin 22): Power Good Input. This pin along with
the PGI check timer serves as a watchdog to monitor the
power-up of the DC/DC converter. The PGI pin must be low
before the PGI check timer expires, otherwise the GATE
pin pulls down and stays latched and a power bad fault
is logged into the FAULT register. The PGI timer is started
after the second power good is latched and its delay is
equal to four times the start-up debounce delay. Connect
to VEE if unused.
PGIO (Pin 28/Pin 21): General Purpose Input/Output.
Open-drain logic output and logic input. Defaults to pull
low a timer delay after the PG pin goes low to indicate a
secondpowergoodoutput.ConfigureaccordingtoTable6.
RAMP (Pin 18/Pin 12): Inrush Current Ramp Control
Pin. The inrush current is set by placing a capacitor (CR)
between the RAMP pin and the drain terminal of the FET.
At start-up, the GATE pin is pulled up by IGATE(UP) until the
pass transistor begins to turn on. A current, IRAMP, then
flows through CR to ramp down the output voltage VOUT.
The value of IRAMP is controlled by the SS pin voltage.
When the SS pin reaches its clamp voltage (2.56V), IRAMP
= 20A. The ramp rate of VOUT and the load capacitor CL
set the inrush current: IINRUSH = (CL/CR) IRAMP.
SCL (Pin 6/Pin 3): Serial Bus Clock Input. Data at the
SDAI pin is shifted in and data at the SDAO pin is shifted
out on rising edges of SCL. This is a high impedance pin
that is generally connected to the output of the incoming
optoisolatordrivenbytheSCLportofthemastercontroller.
An external pull-up resistor or current source is required.
Pull up to INTVCC if unused.
SDAI (Pin 5/Pin 2): Serial Bus Data Input. This is a high
impedance input pin used for shifting in command bits,
data bits and SDAO acknowledge bits. An external pull-up
resistor or current source is required. Normally connected
to the output of the incoming optoisolator that is driven
by the SDA port of the master controller. If the master
controller separates SDAI and SDAO, data read at SDAO
needs to be echoed back to SDAI for proper I2C commu-
nication. Pull up to INTVCC if unused.
SDAO (Pin 4/Pin 1): Serial Bus Data Output. Open-drain
output used for sending data back to the master controller
or acknowledging a write operation. An external pull-up
resistor or current source is required. Normally connected
to the input of the outgoing optoisolator that outputs to
the SDA port of the master controller. In the single-wire
broadcast mode, the SDAO pin sends out selected data
that is encoded with an internal clock.
SENSE (Pin 14/Pin 9): Current Limit Sense Input. Load
current through the external sense resistor (RS) is moni-
tored and controlled by an active current limit amplifier
to 50mV/RS. Once VSENSE reaches 50mV, a circuit breaker
timerstartsandturnsoffthepasstransistorafter530s.In
the event of a catastrophic short circuit, if VSENSE crosses
250mV, a fast response comparator immediately pulls the
GATE pin down to turn off the N-channel FET.
SS (Pin 19/Pin 13): Soft-Start Input. Connect a capaci-
tor to this pin to control the rate of rise of inrush current
(dI/dt) during start-up. An internal 10A current source
charging the external soft-start capacitor (CSS) creates
a voltage ramp. This voltage is converted to a current to
charge the GATE pin up and to ramp the output voltage
down. The SS pin is internally clamped to 2.56V limiting
IGATE(UP) to 11.5A and IRAMP to 20A. If the SS capacitor
is absent, the SS pin ramps from 0V to 2.56V in 220s.
TMR(Pin20/Pin14):DelayTimerInput.Connectacapaci-
tor (CTMR) to this pin to create timing delays at start-up,
when power good outputs pull down, during PGI check
and when auto-retrying after faults (except overvoltage
fault). Internal pull-up currents of 10A and 5A and
pull-down currents of 5A and 12mA configure the delay
periods as multiples of a nominal delay of 256ms CTMR/
F. Delays for start-up and auto-retry following undervolt-
age or power bad fault are the same as the nominal delay.
Delays for sequenced power good outputs are twice of the
nominal delay. Delays for PGI check and auto-retry fol-
lowing overcurrent fault are four times the nominal delay.
(SSOP/QFN)
PIN FUNCTIONS
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LTC4261IGN-2 制造商:LINER 制造商全称:Linear Technology 功能描述:Negative Voltage Hot Swap Controllers with ADC and I2C Monitoring