参数资料
型号: LTC4261CUFD-2#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 电源管理
英文描述: Negative Voltage Hot Swap Controllers with ADC and I2C Monitoring; Package: QFN; No of Pins: 24; Temperature Range: 0°C to +70°C
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24
封装: 4 X 5 MM, LEAD FREE, PLASTIC, QFN-24
文件页数: 7/34页
文件大小: 357K
代理商: LTC4261CUFD-2#PBF
LTC4261/LTC4261-2
15
42612fc
10A until the voltage at TMR reaches 2.56V. CTMR is then
quickly discharged with a 12mA current. The initial delay
expires when TMR is brought below 75mV. The duration
of the start-up delay is given by:
tD = 256ms
CTMR
1F
Ifanyoftheaboveconditionsisviolatedbeforethestart-up
delay expires, CTMR is quickly discharged and the turn-on
sequence is restarted. After all the conditions are validated
throughout the start-up delay, the ON pin is then checked.
If it is high, the FET will be turned on. Otherwise, the FET
will be turned on when the ON pin is raised high or the FET
ON bit D3 in the CONTROL register is set to “1” through
the I2C interface.
The FET turn-on sequence follows by charging an external
capacitor at the SS pin (CSS) with a 10A pull-up current
and the voltage at SS (VSS) is converted to a current
(IGATE(UP)) of 11.5A VSS/2.56V for GATE pull-up. When
the GATE reaches the FET threshold voltage, the inrush
currentstartstoflowthroughtheFETandacurrent(IRAMP)
of 20A VSS/2.56VflowsoutoftheRAMPpinandthrough
an external capacitor (CR) connected between RAMP and
VOUT. The SS voltage is clamped to 2.56V, which cor-
responds to IGATE(UP) = 11.5A and IRAMP = 20A. The
RAMP pin voltage is regulated at 1.1V and the ramp rate
of VOUT determines the inrush current:
IINRUSH = 20A
CL
CR
TheramprateofVSSdeterminesdI/dtoftheinrushcurrent:
dIINRUSH
dt
= 20A
CL
CR
1F
256ms CSS
If CSS is absent, an internal circuit pulls the SS pin from
0V to 2.56V in about 220s.
When VOUT is ramped down to VEE, IGATE returns to
the GATE pin and pulls the GATE up to VGATEH. Figure 4
illustrates the start-up sequence of the LTC4261/
LTC4261-2.
During board insertion and input power step, an internal
clamp turns on to hold the RAMP pin low. Capacitor CF
and resistor RF suppress the noise at the RAMP pin. For
proper operation, RF CR should not exceed 50s. The
recommended value of CF is 3 CR.
Power Good Monitors
When VDS of the pass transistor falls below 1.77V and
GATE pulls above VZ – 1.2V, an internal power good signal
is latched and a series of three delay cycles are started
as shown in Figure 4. When the first delay cycle with a
duration of 2tD expires, the PG pin pulls low as a power
good signal to turn on the first module. When the second
delay cycle (2tD)expires,thePGIOpinpullslowasapower
good signal to turn on the second module. The third delay
cycle with a duration of 4tD is for PGI check. Before the
third delay cycle expires, the PGI pin must be pulled low
by an external supply monitor (such as the LTC2900 in
Figure 2) to keep the FET on. Otherwise, the FET is turned
off and the power bad fault (PBAD) is logged in the FAULT
register. The 2tD timer delay is obtained by charging CTMR
with a 5A current and discharging CTMR with a 12mA
current when TMR reaches 2.56V. For the 4tD timer delay,
the charging and discharging currents of CTMR are both
5A. The power good signals at PG and PGIO are reset in
all FET turn-off conditions except the overvoltage fault.
Turn-Off Sequence and Auto-Retry
In any of the following conditions, the FET is turned off
by pulling down GATE with a 110mA current, and CSS
and CTMR are discharged with 12mA currents.
1. The ON pin is low or the ON bit in the CONTROL reg-
ister is set to 0.
2. The EN pin is high.
3. The voltage at UVL is lower than 2.291V and the volt-
age at UVH is lower than 2.56V (undervoltage fault).
4. The voltage at OV is higher than 1.77V (overvoltage
fault).
5. The voltage at VIN is lower than 9V (VIN undervoltage
lockout).
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LTC4261IGN-2 制造商:LINER 制造商全称:Linear Technology 功能描述:Negative Voltage Hot Swap Controllers with ADC and I2C Monitoring