LTC4266
4266fa
OutputCap
Eachportrequiresa0.22μFcapacrossitsoutputstokeep
theLTC4266stablewhileincurrentlimitduringstartup
oroverload.Commonceramiccapacitorsoftenhavesig-
nificantvoltagecoefficients;thismeansthecapacitance
isreducedastheappliedvoltageincreases.Tominimize
thisproblem,X7Rceramiccapacitorsratedforatleast
100Varerecommended.
ESD/CableDischargeProtection
EthernetportscanbesubjecttosignificantESDevents
whenlongdatacables,eachpotentiallychargedtothou-
sandsofvolts,arepluggedintothelowimpedanceofthe
RJ45jack.Toprotectagainstdamage,eachportrequiresa
pairofclampdiodes;onetoAGNDandonetoVEE(Figure
10).Anadditionalsurgesuppressorisrequiredforeach
LTC4266chipfromVEEtoAGND.Thediodesattheports
steerharmfulsurgesintothesupplyrails,wheretheyare
absorbedbythesurgesuppressorandtheVEEbypass
capacitance. The surge suppressor has the additional
benefitofprotectingtheLTC4266fromtransientsonthe
VEEsupply.
S1B diodes work well as port clamp diodes, and an
SMAJ58AorequivalentisrecommendedfortheVEEsurge
suppressor.
LAYOUTGUIDELINES
StandardpowerlayoutguidelinesapplytotheLTC4266:
placethedecouplingcapsfortheVDDandVEEsupplies
neartheirrespectivesupplypins,usegroundplanes,and
usewidetraceswherevertherearesignificantcurrents.
Themainlayoutchallengeinvolvesthearrangementof
the current sense resistors, and their connections to
theLTC4266.Becausethesenseresistorvaluesarevery
low,layoutparasiticscancausesignificanterrors.Careis
requiredtoachievespecifiedaccuracy,particularlywith
disconnectcurrents.
Figure19illustratestheproblem.Intheexampleonthe
left,twoportshaveloadcurrentsI1andI2thatreturnto
theVEEpowersupplythroughamutualresistanceRM.
RMrepresentsthecombinedresistancesofanytraces,
planes,andviasinthePCBthatI1andI2shareasthey
returntotheVEEsupply.TheLTC4266measuresthevolt-
agedifferencebetweenitsSENSEandVEEpinstosense
thevoltagedropacrossRS1,butastheexampleshows,
RMintroduceserrors.
The example on the right shows how errors can be
minimizedwithagoodlayout.Thecircuitisrearranged
sothatRMnolongeraffectsVS,andtheVEEconnection
totheLTC4266isusedasaKelvinsensetrace.VEEisnot
aperfectKelvinconnectionbecauseallfourportscon-
trolledbytheLTC4266sharethesamesensetrace,and
becausethecurrentthroughthetrace(IEE)isnotzero.
However,astheequationshows,theremainingerrorisa
smalloffsetterm.
Figure20showstwoLTC4266chipscontrollingeightports
(AthoughH).Theportsareseparatedintotwogroups
offour;eachhasitsowntraceonthetopPCBlayerthat
ApplicAtions inForMAtion
RM
+
VS
+
VS
RS1
MUTUAL RESISTANCE
RS2
4266 F19
IEE
–
I1 I2
I1 + I2 + IEE
VS = I1RS1 + I1RM + I2RM
LTC4266
GATE
SENSE
SIGNAL
SCALE ERROR
CROSSTALK ERROR
VEE
RK
RM
RS1
KELVIN SENSE LINE
RS2
IEE
I1 I2
VS = I1RS1 – IEERK
I1 + I2 + IEE
LTC4266
GATE
SENSE
SIGNAL
SMALL OFFSET ERROR
VEE
Figure19.LayoutAffectsCurrentReadbackAccuracy