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参数资料
| 型号： | LTC4302IMS-2#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 12/20页 |
| 文件大小： | 298K |
| 描述： | IC BUFFER 2-WIRE BUS 10-MSOP |
| 标准包装： | 2,500 |
| 类型： | 热交换开关 |
| 应用： | 通用型缓冲器/总线扩展器 |
| 内部开关： | 是 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
LTC4302-1/LTC4302-2
12
sn430212 430212fs
protocol. After the first Data Byte, the master transmits a
second Data Byte, followed by a Stop Bit. The bits of the
second Data Byte are stored in the LTC4302s Register 2.
Table 3 defines the functions of these control bits. The
first 4 MSBs control the input/output configurations of the
two GPIO pins. The next 2 bits control the enabling/
disabling of the card side and backplane side rise time
accelerators respectively. Since the LTC4302 -2 has only
one GPIO pin, DIR1 and OUT CFG1 control its configu-
ration, and DIR2 and OUT CFG2 are ignored. Figure 4
shows a schematic of the two GPIOs and the register bits
that control their operation. The 2 LSBs are not used in
Write operations.
The LTC4302 can also be written with two bytes using the
SMBus Write Word protocol, as shown in Figure 6. The
LTC4302 treats the first two bytes after the Address Byte
(which the Write Word protocol refers to as Command
Code and Data Byte Low ) as the two Data Bytes, and
stores these bytes in Registers 1 and 2 respectively. After
the master transmits the Data Byte High byte, the
LTC4302 acknowledges reception of the byte but ignores
the data contained therein.
OPERATIO
4302 F04
V
CC
DATA IN1
DIR1
OUT CFG1
GPIO1
6
V
CC
DATA IN2
DIR2
OUT CFG2
GPIO2
7
Figure 4. GPIO Circuits and Their Control Bits
Table 3. Register 2 Definition
BIT
NAME
TYPE
FUNCTION
7 (MSB)
DIR2
Read/Write GPIO2 Mode; 0 = Output, 1 = Input*
6
DIR1
Read/Write GPIO1 Mode; 0 = Output, 1 = Input
5
OUT CFG2 Read/Write GPIO2 Output Mode; 0 = Open Drain,
1 = Push-Pull
*
4
OUT CFG1 Read/Write GPIO1 Output Mode; 0 = Open Drain,
1 = Push-Pull
3
OUTACC Read/Write Card Side Rise Time Accelerator
Contol; 0 = Disabled, 1 = Active
2
INACC Read/Write Backplane Side Rise Time Accelerator
Control; 0 = Disabled, 1 = Active
1
NA
Read Only Never Used, Always 1
0
NA
Read Only Never Used, Always 1
Default State (MSB First): 00000011
OUT CFG1 has no effect when DIR1 = 1; OUT CFG2 has no effect when
DIR2 = 1.
*DIR2 and OUT CFG2 apply only to the LTC4302-1; there is no GPIO2 for
the LTC4302-2, so these bits are meaningless in this case.
START
ACK
11 a4 - a0
WR
d7 - d0
1
1
7
1
8
S
0
0
ACK
1
S
0
DATA
BYTE 1
d7 - d0
8
ACK
1
S
0
DATA
BYTE 2
SLAVE
ADDRESS
STOP
1
4302 F05
START
ACK
11 a4 - a0
WR
d7 - d0
1
1
7
1
8
S
0
0
ACK
1
S
0
COMMAND
CODE
d7 - d0
8
ACK
1
S
0
DATA
BYTE LOW
SLAVE
ADDRESS
XXXXXXXX
8
ACK
1
S
0
DATA
BYTE HIGH
STOP
1
4302 F06
Figure 5. Writing Two Bytes
Figure 6. Writing Two Bytes Using SMBus Write Word Protocol
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