参数资料
型号: LTC4308CDD#PBF
厂商: Linear Technology
文件页数: 3/16页
文件大小: 168K
描述: IC BUS BUFFER LV 8-DFN
产品培训模块: LTC4310 - Hot-Swappable I²C Isolators
标准包装: 121
类型: 热交换开关
应用: 通用型缓冲器/总线扩展器
内部开关:
电源电压: 2.3 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
供应商设备封装: 8-DFN-EP(3x3)
包装: 管件
LTC4308
3
4308f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX    UNITS
t
IDLE
Bus Idle Time
l   55
95
175
V
THR_EN
ENABLE Threshold Voltage
ENABLE Rising Edge
l
0.45
0.6
0.75
V
V
THR_EN(HYST)
ENABLE Threshold Voltage Hysteresis
(Note 3)
35
mV
I
ENABLE
ENABLE Input Current
ENABLE from 0V to V
CC
l
0.1
?
t
PLH_EN
ENABLE Delay Off-On
(Figure 1)
95
t
PHL_EN
ENABLE Delay On-Off
(Note 3), (Figure 1)
10
ns
t
PLH_READY
 
READY Delay Off-On
(Note 3), (Figure 1)
10
ns
t
PHL_READY
READY Delay On-Off
(Note 3), (Figure 1)
10
ns
V
OL_READY
READY Output Low Voltage
I
READY
 = 3mA, V
CC
 = 2.3V
l
0.4
V
I
OFF_READY
READY Off Leakage Current
V
CC
 = READY = 5.5V
l
0.1
?
Prop Delay and Rise-Time Accelerators
t
PHL
SDA/SCL Propagation Delay High to Low
C
LOAD
 = 50pF , 2.7k to V
CC
 on SDA, SCL,
(Notes 2, 3), (Figure 1)
70
ns
t
PLH
SDA/SCL Propagation Delay Low to High
C
LOAD
 = 50pF , 2.7k to V
CC
 on SDA, SCL,
(Notes 2, 3), (Figure 1)
10
ns
t
RISE
SDA/SCL Transition Time Low to High
C
LOAD
 = 100pF , 10k to V
CC
 on SDA, SCL,
(Notes 3, 4), (Figure 1)
30
300
ns
t
FALL
SDA/SCL Transition Time High to Low
C
LOAD
 = 100pF , 10k to V
CC
 on SDA, SCL,
(Notes 3, 4), (Figure 1)
30
300
ns
I
PULLUPAC
Transient Boosted Pull-Up Current
Positive Transition > 0.8V/約 on SDAOUT ,
SCLOUT (Note 5)
5
8
mA
Input-Output Connection
V
OS
Input to Output Offset Voltage (OUT  IN)
2.7k to V
CC
 on SDAOUT , SCLOUT ,
SDAIN = SCLIN = 0.2V
l
250
300
380
mV
2.7k to V
CC
 on SDAOUT , SCLOUT ,
SDAIN = SCLIN = 0.4V , V
CC
 = 5.5V
l
250
350
450
mV
Output to Input Offset Voltage (IN  OUT)
2.7k to V
CC
 on SDAIN, SCLIN,
SDAOUT = SCLOUT = 0.4V
l    150
200
300
mV
2.7k to V
CC
 on SDAIN, SCLIN,
SDAOUT = SCLOUT = 0.4V , V
CC
 = 5.5V
l    150
250
350
mV
V
THR
SDAOUT , SCLOUT Logic Input Threshold Voltage  V
CC
 e 2.9V
V
CC
 < 2.9V
1.4
1.1
1.65
1.35
1.9
1.6
V
V
SDAIN, SCLIN Logic Input Threshold Voltage
SDAIN, SCLIN Rising Edge, V
CC
 = 2.3V , 5.5V
0.45
0.6
0.75
V
V
THR(HYST)
SDAOUT , SCLOUT Logic Input Threshold Voltage
Hysteresis
(Note 3)
50
mV
SDAIN, SCLIN Logic Input Threshold Voltage
Hysteresis
(Note 3)
35
mV
C
IN
Digital Input Capacitance SDAIN, SDAOUT ,
SCLIN, SCLOUT
(Note 3)
10
pF
I
LEAK
Input Leakage Current
SDA, SCL Pins
l
?
V
OL
Output Low Voltage
SDAOUT , SCLOUT Pins, I
SINK
 = 4mA,
SDAIN = SCLIN = 0V , V
CC
 = 2.7V
l
0
400
mV
2.7k to V
CC
 on SDAOUT , SCLOUT ,
SDAIN = SCLIN = 0V
l
250
300
380
mV
V
ILMAX
Buffer Input Logic Low Voltage
SDAOUT , SCLOUT Pins
l
1.2
V
 
The l denotes the speci cations which apply over the full operating
temperature range, otherwise speci cations are at T
A
 = 25癈. V
CC
 = 3.3V, unless otherwise noted.
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