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参数资料
| 型号： | LTC4315IMS#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 19/20页 |
| 文件大小： | 0K |
| 描述： | IC 2WIRE BUS BUFFER 12MSOP |
| 标准包装： | 37 |
| 类型： | 2线总线缓冲器 |
| Tx/Rx类型： | I²C Logic |
| 电容 - 输入： | 10pF |
| 电源电压： | 2.9 V ~ 5.5 V |
| 电流 - 电源： | 8.1mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-TSSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 12-MSOP |
| 包装： | 管件 |
LTC4315
8
4315f
OPERATION
The Block Diagram shows the major functional blocks
of the LTC4315. The LTC4315 is a high noise margin bus
buffer which provides capacitance buffering for I2C signals.
Capacitance buffering is achieved by using back to back
buffers on the clock and data channels, which isolate
the SDAIN and SCLIN capacitances from the SDAOUT
and SCLOUT capacitances respectively. All SDA and SCL
pins are fully bidirectional. The high noise margin allows
the LTC4315 to operate with non-compliant I2C devices
that drive a high VOL, permits a number of LTC4315s to
be connected in series and improves the reliability of I2C
communications in large noisy systems. When enabled,
rise time accelerator (RTA) pull-up currents (IRTA) turn on
during rising edges to reduce bus rise time. In a typical
application, the input bus is pulled up to VCC and the
output bus is pulled up to VCC2, although these are not
requirements. VCC is the primary power supply to the
LTC4315. VCC and VCC2 serve as the input and output side
rise time accelerator supplies respectively. Grounding VCC2
selectively disables the output side RTAs.
When the LTC4315 first receives power on its VCC pin, it
starts out in an under voltage lockout mode (UVLO) until
its VCC exceeds 2.7V. The buffers and RTAs are disabled
and the LTC4315 ignores the logic state of its clock and
data pins. During this time the precharge circuit forces a
nominal voltage of 1V on the SDA and SCL pins through
200k resistors.
Once the LTC4315 exits UVLO and its ENABLE pin has
been asserted high, it monitors the clock and data pins
for a stop bit or a bus idle condition. When a combination
of either condition is detected simultaneously on the input
and output sides, the LTC4315 activates the connections
between SDAIN and SDAOUT, and SCLIN and SCLOUT
respectively, asserts READY high and deactivates the
precharge circuit. If ACC is low or open, RTAs are also
enabled at this time. VCC2 transitions from a high to a low
or vice versa across a 1.8V threshold cause the LTC4315
to disable the buffers and RTAs and to ignore the clock
and data pins for 95μs after that transition. A stop bit or
bus idle is required on both sides to reactivate the buffers
and RTAs. The precharge circuit is not affected by VCC2.
When a SDA/SCL pin is driven below the VIL level, the
buffers are turned on and the logic low level is propagated
though the LTC4315 to the other side. A high occurs when
all devices on the input and output sides release high.
Once the bus voltages rise above the VIL level, the buffers
are turned off. The RTAs are turned on at a slightly higher
voltage. The RTAs accelerate the rising edges of the SDA/
SCL inputs and outputs up to voltages of 0.9 VCC and
0.9 VCC2 respectively, provided that the busses on their
own are rising at a minimum rate of 0.4V/μs as determined
by internal slew rate detectors. ACC is a three-state input
that controls the RTA pull-up current strength IRTA.
The LTC4315 detects a bus stuck low (fault) condition
when both clock and data busses are not simultaneously
high at least once in 45ms. When a stuck bus occurs, the
LTC4315 asserts the FAULT flag. If DISCEN is tied high, the
LTC4315 also disconnects the input and output sides and
after waiting at least 40μs, generates up to sixteen 5.5kHz
clock pulses on the SCLOUT pin and a stop bit to attempt
to free the stuck bus. Should the stuck bus release high
during this period, clock generation is terminated and the
FAULT flag is cleared.
If DISCEN is tied low, a stuck bus event only causes FAULT
flag assertion. Disconnection of the input and output sides
and clock generation are not done. Once the stuck bus
recovers and FAULT flag has been cleared, connection is
re-established between the input and output after a stop
bit or bus idle condition is detected. Toggling the ENABLE
pin after a fault condition has occurred forces a connec-
tion between the input and output. When powering into
a stuck low condition, the input and output sides remain
disconnected. After the timeout period, a stuck low fault
condition is detected and the behavior is as described
previously.
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