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参数资料
| 型号： | LTC5100EUF#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 33/52页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER VCSEL 3.2GBPS 16QFN |
| 标准包装： | 2,500 |
| 类型： | 激光二极管驱动器 |
| 数据速率： | 3.2Gbps |
| 通道数： | 1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 54mA |
| 电流 - 调制： | 12mA |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-WQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN（4x4） |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
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LTC5100
OPERATIO
Table 6. Effective Base Addresses for Various Sized EEPROMs
GENERIC PART NUMBER
Bits
Bytes
Device Address (Binary)
Word Address Space (Binary)
LTC5100 Generates
Device Address
LTC5100 Generates
Word Address
Effective Base Address
Comments
24LC00
128
16
1010xxx.
xxxx_nnnn
1010_111.
= 0xAE
0110_0000
= 0x60
0000_0000
= 0x00
Minimum Size
EEPROM.
Loads Every
Byte in the
24LC01B
1k
128
1010xxx.
xnnn_nnnn
1010_111.
= 0xAE
0110_0000
= 0x60
0110_0000
= 0x60
EEPROM Not Big
Enough for GBIC
ID. LTC5100
Loads from 0x60
24LC02B
2k
256
1010xxx.
nnnn_nnnn
1010_111.
= 0xAE
0110_0000
= 0x60
0110_0000
= 0x60
Standard GBIC
EEPROM.
Smallest EEPROM
That is Big Enough
24LC04B
4k
512
1010.xxa
nnnn_nnnn
1010_111.
= 0xAE
0110_0000
= 0x60
0001_0110_0000
= 0x160
LTC5100 Loads
from an Area
Outside the GBIC
ID Data Area
24LC16B
16k
2048
1010cba.
nnnn_nnnn
1010_111.
= 0xAE
0110_0000
= 0x60
0111_0110_0000
= 0x760
LTC5100 Loads
from an Area
Outside the GBIC
ID Data Area
EEPROM.
to 0x6F
to Hold the LTC5100
Data and the GBIC ID.
LTC5100 Loads from
0x60 to 0x6F, the First
16 Bytes of the
Vendor Area
Microprocessor Controlled Operation
An external microprocessor or a test computer can take
full control of the LTC5100 by setting the Operating_mode
bit. When this bit is set, the LTC5100 stops searching for
an external EEPROM and takes commands from the mi-
croprocessor. It is even possible to combine standalone
and microprocessor controlled modes. If an EEPROM is
present, the LTC5100 will load its configuration registers
from the EEPROM at power-up. A microprocessor or test
computer can then read and write the LTC5100 registers
at will.
The primary purpose of the Operating_mode bit is to stop
the LTC5100’s EEPROM load attempts. Once the LTC5100
has loaded itself from an EEPROM (if present), it is not
technically necessary to set the Operating_mode bit to
communicate with the LTC5100.
The LTC5100 attempts to read the EEPROM every 64ms
until it successfully loads its registers or until the
Operating_mode bit is set. There is a finite chance that the
microprocessor and the LTC5100 will generate an I 2 C bus
collision if an EEPROM load attempt coincides with the
microprocessor’s attempt to access the LTC5100. In this
case, the microprocessor will receive a NACK (not-ac-
knowledged) response to its transmissions. The micro-
processor needs only to cease transmission in accordance
with the I 2 C protocol and try again. If the microprocessor
makes this second attempt within 64ms (typical), it is
guaranteed not to collide with the LTC5100.
sn5100 5100fs
33
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