参数资料
型号: LTC5100EUF#TRPBF
厂商: Linear Technology
文件页数: 6/52页
文件大小: 0K
描述: IC DRIVER VCSEL 3.2GBPS 16QFN
标准包装: 2,500
类型: 激光二极管驱动器
数据速率: 3.2Gbps
通道数: 1
电源电压: 3.135 V ~ 3.465 V
电流 - 电源: 54mA
电流 - 调制: 12mA
工作温度: -40°C ~ 85°C
封装/外壳: 16-WQFN 裸露焊盘
供应商设备封装: 16-QFN(4x4)
包装: 带卷 (TR)
安装类型: 表面贴装
LTC5100
ELECTRICAL CHARACTERISTICS The q denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T A = 25 ° C. V DD = V DD(HS) = 3.3V, I S = 24mA; I M = 12mA (I MPP = 24mA); 49.9 ? , 1%
resistor from SRC (Pin 14) to MODA (Pin 11); 50 ? , 1% load AC coupled to MODB (Pin 10); 10nF, 10% capacitor from SRC (Pin 14) to
V SS ; Cml_en = 0, Lpc_en = 1, transmitter enabled, unless otherwise noted. Test circuit in Figure 5.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SCL, SDA
SCL, SDA Input Low Voltage, V IL
–0.5
0.3 ?
V
V DD
SCL, SDA Input High Voltage, V IH
SCL, SDA Input Low Current (Note 21)
SCL, SDA Input High Current (Note 21)
V SDA , V SCL = 0.1 ? V DD
V SDA , V SCL = 0.9 ? V DD
0.7 ?
V DD
–100
–100
V DD +
0.5
V
μ A
μ A
SCL, SDA Output Low Voltage
Hysteresis
I OL = 3mA
0
280
0.4
V
mV
Serial Interface Timing (Note 20)
SCL Clock Frequency
Hold Time (Repeated) START Condition. After This
Period the First Clock Pulse is Generated
Low Period of the SCL Clock
High Period of the SCL Clock
Set-Up Time for a Repeated START Condition
4
4.7
4
4.7
100
kHz
μ s
μ s
μ s
μ s
Data Hold Time
0
3.45
μ s
Data Set-Up Time
Input Rise Time of Both SDA and SCL Signals
Output Fall Time of SCL and SDA from V IH(MIN) to
V IL(MAX) with a Bus Capacitance from 10pF to 400pF
Set-Up Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Capacitive Load for Each Bus Line
Noise Margin at the LOW Level for Each Connected
Device (Including Hysteresis)
Noise Margin at the HIGH Level for Each Connected
250
4
4.7
0.1 ?
V DD
0.2 ?
1000
300
400
ns
ns
ns
μ s
μ s
pF
V
V
Device (Including Hysteresis)
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: The quiescent V DD and V DD(HS) currents refer to the current with
zero SRC pin current (i.e., the laser is operating with zero bias current and
zero modulation current). The total power supply current is the quiescent
current plus the SRC pin current, I S , plus any current sinked from IN + and
IN – .
Note 3: The peak transient voltage at the IN + and IN – pins must not
exceed the range of –300mV to V DD(HS) + 300mV.
Note 4: When Cml_en = 0 (not in CML mode), the termination is 100 ?
differential with 50k common mode to V DD(HS) /2.
Note 5: The common mode input resistance is measured relative to
V DD(HS) /2 with the inputs tied together.
Note 6: When Cml_en = 1 (CML mode), the termination is nominally 50 ?
to V DD(HS) on each of the IN + and IN – pins.
V DD
Note 7: The SRC pin current can be programmed to near zero in each
range, but the recommended minimum operating level is 1/16 of full scale.
Note 8: The laser bias current is the average current delivered to the laser.
It is equal to the SRC pin current minus the average modulation current at
the MODA and MODB pins, or I B = I S – I M . Full scale for the bias current
therefore depends on Is_rng and the actual modulation current.
Note 9: The MODA and MODB pins are connected on-chip. The modulation
current refers to the sum of the currents on these pins. I M refers to the
total average current at the MODA and MODB pins. I MPP refers to the total
peak-to-peak modulation current at the MODA and MODB pins. I MPP differs
from the laser modulation current, I MOD . I MPP splits between the laser and
the termination resistor according to I MOD = I MPP ? R T /(R T + R LD ), where
R T is the value of the termination resistor and R LD is the dynamic
resistance of the laser diode.
sn5100 5100fs
6
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