参数资料
型号: LTC6410IUD-6#PBF
厂商: Linear Technology
文件页数: 2/16页
文件大小: 0K
描述: IC AMP DIFF IF 16-QFN
标准包装: 121
放大器类型: 差分
电路数: 1
输出类型: 差分
转换速率: 1500 V/µs
-3db带宽: 1.4GHz
电压 - 输入偏移: 400µV
电流 - 电源: 125mA
电流 - 输出 / 通道: 42mA
电压 - 电源,单路/双路(±): 2.8 V ~ 5.5 V,±1.4 V ~ 2.75 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-WFQFN 裸露焊盘
供应商设备封装: 16-QFN-EP(3x3)
包装: 管件
产品目录页面: 1323 (CN2011-ZH PDF)
LTC6410-6
10
64106fa
PIN FUNCTIONS
V(Pins 1, 4, 9, 12, 17): Negative Power Supply (Normally
Tied to Ground). All 5 pins must be tied to the same voltage.
Vmaybe tied to a voltage other than ground as long as the
voltage between V+ and Vis 2.8V to 5.5V. If the Vpins
are not tied to ground, bypass each with 680pF and 0.1μF
capacitors as close to the package as possible.
VBIAS (Pin 2): This pin sets the input and output com-
mon mode voltage by driving the +IN and –IN through a
buffer with a high output resistance of 1k. If the part is
AC-coupled at the input, the VBIAS will set the VINCM and
therefore the VOUTCM voltage. If the part is DC-coupled at
the input, VBIAS should be left oating. Internal resistors
bias VBIAS to 1.4V on a 3V supply.
V+ (Pins 3, 5, 8, 10):
Positive Power Supply. All 4 pins
must be tied to the same voltage. Split supplies are pos-
sible as long as the voltage between V+ and Vis 2.8V to
5.5V. Bypass capacitors of 680pF and 0.1μF as close to the
part as possible should be used between supplies.
+OUT, –OUT (Pins 6, 7): Outputs. These pins each have
internal series termination resistors forming a differential
output resistance.
SHDN (Pin 11): This pin is internally pulled high by a typi-
cally 30k resistor to V+. By pulling this pin low the supply
current will be reduced to typically 3mA. See DC Electrical
Characteristics table for the specic logic levels.
–TERM (Pin 13): Negative Input Termination. When tied
directly to –IN, it provides an active 50Ω differential ter-
mination when +TERM is also tied directly to +IN.
–IN (Pin 14): Negative Input. This pin is normally tied to
–TERM, the input termination pin. If AC-coupled, this pin
will self bias by VBIAS.
+IN (Pin 15): Positive Input. This pin is normally tied to
+TERM, the input termination pin. If AC-coupled, this pin
will self bias by VBIAS.
+TERM (Pin 16): Positive Input Termination. When tied
directly to +IN, it provides an active 50Ω differential ter-
mination when –TERM is also tied directly to –IN.
Exposed Pad (Pin 17): V. The Exposed Pad must be
soldered to the PCB metal.
BLOCK DIAGRAM
64106 BD
–IN
+IN
1k
6.4k
V+
V
VBIAS
REXT
(OPT)
REXT
(OPT)
CEXT
(OPT)
CEXT
(OPT)
RO
11Ω
RO
11Ω
–OUT
+OUT
5.7k
RT
110Ω
RT
110Ω
+
+
+TERM
–IN
+IN
0.1μF
–TERM
+1
AV = 2.7V/V
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