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| 型号： | LTC6800HDD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 14/14页 |
| 文件大小： | 0K |
| 描述： | IC OP AMP INSTR R-R I/O 8-DFN |
| 标准包装： | 2,500 |
| 放大器类型： | 仪表 |
| 电路数： | 1 |
| 输出类型： | 满摆幅 |
| 转换速率： | 0.2 V/µs |
| 增益带宽积： | 200kHz |
| 电流 - 输入偏压： | 4nA |
| 电压 - 输入偏移： | 100µV |
| 电流 - 电源： | 1.3mA |
| 电压 - 电源，单路/双路(±)： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 供应商设备封装： | 8-DFN-EP（3x3） |
| 包装： | 带卷 (TR) |
LTC6800
6800fb
Input Current
Whenever the differential input VIN changes, CH must be
charged up to the new input voltage via CS. This results
in an input charging current during each input sampling
period. Eventually, CH and CS will reach VIN and, ideally,
the input current would go to zero for DC inputs.
In reality, there are additional parasitic capacitors which
disturb the charge on CS every cycle even if VIN is a DC
voltage. For example, the parasitic bottom plate capacitor
on CS must be charged from the voltage on the REF pin
to the voltage on the –IN pin every cycle. The resulting
input charging current decays exponentially during each
input sampling period with a time constant equal to RSCS.
If the voltage disturbance due to these currents settles
before the end of the sampling period, there will be no
errors due to source resistance or the source resistance
mismatch between –IN and +IN. With RS less than 10k,
no DC errors occur due to this input current.
In the Typical Performance Characteristics section of this
data sheet, there are curves showing the additional error
from nonzero source resistance in the inputs. If there are
no large capacitors across the inputs, the amplifier is
less sensitive to source resistance and source resistance
mismatch. When large capacitors are placed across the
inputs, the input charging currents previously described
result in larger DC errors, especially with source resistor
mismatches.
Power Supply Bypassing
TheLTC6800usesasampleddatatechniqueand,therefore,
contains some clocked digital circuitry. It is, therefore,
sensitive to supply bypassing. A 0.1F ceramic capacitor
must be connected between Pin 8 (V+) and Pin 4 (V–) with
leads as short as possible.
applicaTions inForMaTion
–
+
–
+
VIN
V+IN
VOUT
V–IN
3
8
5V
4
5
6
7
2
–
+
–
+
VIN
V+IN
VOUT
V–IN
VREF
3
8
5V
0V < V–IN < 5V AND V–IN – VREF < 5.5V
0V < V+IN < 5V AND V+IN – VREF < 5.5V
0V < VIN + VREF < 3.7V
UNITY GAIN
–
+
–
+
VIN
V+IN
VOUT
V–IN
3
8
5V
4
5
6
7
2
0V < V+IN < 5V
0V < V–IN < 5V
0V < VIN < 3.7V
VOUT = VIN
UNITY GAIN
NONUNITY GAIN
4
5
6 R2
R1
7
2
VOUT = 1 +
VIN + VREF
R2
R1
0V < V–IN < 5V AND V–IN – VREF < 5.5V
0V < V+IN < 5V AND V+IN – VREF < 5.5V
0V < VIN + VREF < 3.7V
VOUT = VIN + VREF
–
+
–
+
VIN
V+IN
VOUT
V–IN
3
6800 F01
8
0V < V–IN < 5V AND V–IN – VREF < 5.5V
0V < V+IN < 5V AND V+IN – VREF < 5.5V
0V < VIN + VREF < 3.7V
NONUNITY GAIN
4
5
6 R2
R1
7
2
VOUT = 1 +
(VIN + VREF)
R2
R1
Figure 1
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