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| 型号： | LTC693CSW#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 14/20页 |
| 文件大小： | 0K |
| 描述： | IC MPU SUPERVISRY CIRCUIT 16SOIC |
| 标准包装： | 47 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 140 ms |
| 电压 - 阀值： | 4.4V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
LTC692/LTC693
APPLICATIONS INFORMATION
Example 2: The circuit in Figure 9 can be used to measure
the regulated 5V supply to provide early warning of power
failure. Because of variations in the PFI threshold, this
circuit requires adjustment to ensure the PFI comparator
trips before the reset threshold is reached. Adjust R5 such
that the PFO output goes low when the V CC supply reaches
the desired level (e.g., 4.6V).
Monitoring the Status of the Battery
C3 can also monitor the status of the memory backup
battery (Figure 10). If desired, the CE OUT can be used to
apply a test load to the battery. Since CE OUT is forced high
in battery backup mode, the test load will not be applied
to the battery while it is in use, even if the microprocessor
is not powered.
5V
Watchdog Timer
The LTC692/LTC693 provide a watchdog timer function to
monitor the activity of the microprocessor. If the micropro-
cessor does not toggle the watchdog input (WDI) within
a selected timeout period, RESET is forced to active low
for a minimum of 140ms. The reset active time is adjust-
able on the LTC693. Since many systems cannot service
the watchdog timer immediately after a reset, the LTC693
has longer timeout period (1.0 second minimum) right
after a reset is issued. The normal timeout period (70ms
minimum) becomes effective following the ?rst transition
of WDI after RESET is inactive. The watchdog timeout
period is ?xed at a 1.0 second minimum on the LTC692.
Figure 11 shows the timing diagram of watchdog timeout
period and reset active time. The watchdog timeout period
is restarted as soon as RESET is inactive. When either a
high-to-low or low-to-high transition occurs at the WDI pin
3V
R1
1M
R2
V BATT
PFI
V CC
LTC693
PFO
LOW-BATTERY SIGNAL
TO μP I/O PIN
prior to timeout, the watchdog timer is reset and begins
to timeout again. To ensure the watchdog timer does not
timeout, either a high-to-low or low-to-high transition
on the WDI pin must occur at or less than the minimum
1M
CE OUT
R L
20K
OPTIONAL TEST LOAD
CE IN
GND
692_3 ? F10
I/O PIN
timeout period. If the input to the WDI pin remains either
high or low, reset pulses will be issued every 1.6 seconds
typically. The watchdog timer can be deactivated by ?oat-
ing the WDI pin. The timer is also disabled when V CC falls
below the reset voltage threshold or V BATT .
Figure 10. Backup Battery Monitor with Optional Test Load
V CC = 5V
WDI
t 1 = RESET ACTIVE TIME
WDO
RESET
t 1
t 2
t 2 = NORMAL WATCHDOG TIME-OUT PERIOD
t 3 = WATCHDOG TIME-OUT PERIOD IMMEDIATELY
AFTER A RESET
t 3
t 1
692_3 ? F11
Figure 11. Watchdog Timeout Period and Reset Active Time
0692fb
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