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参数资料
| 型号： | LTC695IN-3.3#TRPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP16 |
| 封装： | 0.300 INCH, LEAD FREE, PLASTIC, DIP-16 |
| 文件页数： | 18/20页 |
| 文件大小： | 189K |
| 代理商： | LTC695IN-3.3#TRPBF |
LTC694-3.3/LTC695-3.3
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PIN FUNCTIONS
BATT ON: Battery On Logic Output from Comparator C2.
BATT ON goes low when VOUT is internally connected to
VCC. The output typically sinks 25mA and can provide
base drive for an external PNP transistor to increase the
output current above the 50mA rating of VOUT. BATT ON
goes high when VOUT is internally switched to VBATT.
CE IN: Logic Input to the Chip
_
Enable Gating Circuit. CE IN
can be derived from microprocessor’s address line and/or
decoder output. See the Applications Information section
and Figure 5 for additional information.
CE OUT: Logic Output on the Chip
_
Enable Gating Circuit.
When VCC is above the reset voltage threshold, CE OUT is
a buffered replica of CE IN. When VCC is below the reset
voltage threshold CE OUT is forced high (see Figure 5).
GND: Ground Pin.
LOW
_
LINE: Logic Output from Comparator C1. LOW
_
LINE
indicates a low line condition at the VCC input. When VCC
falls below the reset voltage threshold (2.90V typically),
LOW
_
LINE goes low. As soon as VCC rises above the reset
voltage threshold, LOW
_
LINE returns high (see Figure 1).
LOW
_
LINE goes low when VCC drops below VBATT (see
Table 1).
OSC IN: Oscillator Input. OSC IN can be driven by an
external clock signal or an external capacitor can be con-
nected between OSC IN and GND when OSC SEL is forced
low. In this configuration the nominal reset active time and
watchdog timeout period are determined by the number
of clocks or set by the formula (see the Applications In-
formation section). When OSC SEL is high or floating, the
internal oscillator is enabled and the reset active time is
fixed at 200ms typical for the LTC695-3.3. OSC IN selects
between the 1.6 seconds and 100ms typical watchdog
timeout periods. In both cases, the timeout period im-
mediately after a reset is 1.6 seconds typical.
OSC SEL: Oscillator Selection Input. When OSC SEL is
high or floating, the internal oscillator sets the reset active
time and watchdog timeout period. Forcing OSC SEL low,
allows OSC IN to be driven from an external clock signal
or an external capacitor can be connected between OSC
IN and GND.
PFI: Power Failure Input. PFI is the noninverting input
to the power-fail comparator, C3. The inverting input is
internally connected to a 1.3V reference. The power failure
output remains high when PFI is above 1.3V and goes
low when PFI is below 1.3V. Connect PFI to GND or VOUT
when C3 is not used.
PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When VCC is lower than VBATT, C3 is shut down and
PFO is forced low.
RESET: Active High Logic Output. It is the inverse of
RESET.
RESET: Logic Output for μP Reset Control. Whenever VCC
falls below either the reset voltage threshold (2.90V, typi-
cally) or VBATT, RESET goes active low. After VCC returns
to 3.3V, the reset pulse generator forces RESET to remain
active low for a minimum of 140ms. When the watchdog
timer is enabled but not serviced prior to a preset timeout
period, the reset pulse generator also forces RESET to ac-
tive low for a minimum of 140ms for every preset timeout
period (see Figure 11). The reset active time is adjustable
on the LTC695-3.3. An external push-button reset can be
used in connection with the RESET output. See Push-But-
ton Reset in the Applications Information section.
VBATT: Back-Up Battery Input. When VCC falls below VBATT,
auxiliary power connected to VBATT, is delivered to VOUT
through PMOS switch, M2. If back-up battery or auxiliary
power is not used, VBATT should be connected to GND.
VCC: 3.3V Supply Input. The VCC pin should be bypassed
with a 0.1μF capacitor.
VOUT: Voltage Output for Backed Up Memory. Bypass with
a capacitor of 0.1μF or greater. During normal operation,
VOUT obtains power from VCC through an NMOS power
switch, M1, which can deliver up to 50mA and has a typical
on resistance of 5Ω. When VCC is lower than VBATT, VOUT
is internally switched to VBATT. If VOUT and VBATT are not
used, connect VOUT to VCC.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC695INPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:Microprocessor Supervisory Circuits |
| LTC695IN-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:Microprocessor Supervisory Circuits |
| LTC695IS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Power Supply Supervisor |
| LTC695IS-3.3 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Power Supply Supervisor |
| LTC695ISW | 功能描述:IC MPU SUPERVISRY CIRCUIT 16SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:1 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:开路漏极或开路集电极 复位:高有效 复位超时:- 电压 - 阀值:1.8V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:6-TSOP（0.059"，1.50mm 宽）5 引线 供应商设备封装:5-TSOP 包装:剪切带 (CT) 其它名称:NCP301HSN18T1GOSCT |
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