参数资料
型号: LTC6991CDCB#TRMPBF
厂商: Linear Technology
文件页数: 10/24页
文件大小: 0K
描述: IC OSC SILICON 977HZ 6-DFN
产品培训模块: TimerBlox Family Timing Devices
产品目录绘图: LTC699_DFN
特色产品: LTC?6991 Silicon Oscillator
TimerBlox?
标准包装: 1
系列: TimerBlox®
类型: 振荡器 - 硅
频率: 29.1µHz ~ 977Hz
电源电压: 2.25 V ~ 5.5 V
电流 - 电源: 135µA
工作温度: 0°C ~ 70°C
封装/外壳: 6-WFDFN 裸露焊盘
包装: 标准包装
供应商设备封装: 6-DFN-EP(2x3)
安装类型: 表面贴装
配用: DC1562A-B-ND - BOARD EVAL LTC6991
其它名称: LTC6991CDCB#TRMPBFDKR
LTC6991
18
6991fb
1. Connect the bypass capacitor, C1, directly to the V+ and
GND pins using a low inductance path. The connection
from C1 to the V+ pin is easily done directly on the top
layer. For the DFN package, C1’s connection to GND is
also simply done on the top layer. For the TSOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1μF ceramic capacitor.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place RSET as close as possible to the SET pin and
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
4. Connect RSET directly to the GND pin. Using a long path
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
6991 F18
LTC6991
RST
GND
SET
OUT
V+
DIV
C1
0.1μF
R1
R2
RSET
V+
DIV
SET
OUT
GND
RST
C1
R1
R2
V+
RSET
DFN PACKAGE
RST
GND
SET
OUT
V+
DIV
R2
V+
RSET
TSOT-23 PACKAGE
R1
C1
Figure 18. Supply Bypassing and PCB Layout
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