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参数资料
| 型号： | LTH2911HDDB-5#TR |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封装： | 3 X 2 MM, PLASTIC, MO-229, DFN-8 |
| 文件页数： | 17/20页 |
| 文件大小： | 245K |
| 代理商： | LTH2911HDDB-5#TR |
LTC2911
6
2911f
PIN FUNCTIONS
ADJ: Adjustable Voltage Monitor Input. Input to a voltage
monitor comparator with a 0.5V nominal threshold. Tie
to V1 if unused.
Exposed Pad (DFN Only): Exposed pad may be left open
or connected to device ground.
GND: Device Ground.
PFI: Power-Fail Voltage Monitor Input. Input to the power-
fail comparator with a 500mV threshold at the falling
edge and a 515mV threshold at the rising edge, giving
a 3% hysteresis for noise rejection. Tie to V1 or GND if
unused.
PFO: Power-Fail Logic Output. This pin asserts low when
the PFI input voltage is below its threshold and goes high
when the PFI input voltage is above its threshold. This pin
provides a weak pull-up current to V1. This current is typi-
cally 29A at V1 = 3.3V. The pin can be pulled to voltages
higher than V1 by external pull-up resistors. PFO provides
an early warning signal of a system power failure.
RST: Reset Logic Output. This pin asserts low when any
of the V1, V2, or ADJ inputs are below their reset thresh-
olds. Pulls high when all the monitored inputs are above
their thresholds for longer than a timeout period. This pin
provides a weak pull-up current to V1. This current is typi-
cally 29A at V1 = 3.3V. The pin can be pulled to voltages
higher than V1 by external pull-up resistors. The status of
RST can be latched by holding the TMR pin at GND.
TMR: Reset Timeout Control. Attach an external capacitor,
CTMR, to GND to set a reset timeout period of 9.4ms/nF. A
low leakage ceramic capacitor is recommended for timer
accuracy. A 2.2nF capacitor generates a 20ms timeout.
Leaving the TMR pin open without a capacitor generates
a minimum timeout of approximately 400s which will
vary depending on the parasitic capacitance on the pin.
Tying this pin to V1 enables the internal 200ms timeout.
Pulling this pin to GND latches the reset state.
V1: 3.3V Monitor and Power Supply Input. V1 is an accu-
rate 3.3V, –5% undervoltage supply monitor. The internal
VCC is generated from the greater of the voltages at the
V1 and V2 inputs for the LTC2911-1/LTC2911-2/LTC2911-
3/LTC2911-4options.TheLTC2911-5optionalwaysderives
its power supply from the V1 pin. Bypass this pin to GND
with a 0.1F (or greater) capacitor for the LTC2911-2
through LTC2911-5.
V2: Voltage Monitor and Power Supply Input. V2 is a
–5% undervoltage supply monitor for a 5V, 2.5V, 1.8V
or 1.2V supply for the LTC2911-1/LTC2911-2/LTC2911-
3/LTC2911-4 options, respectively. Because the internal
VCC is generated from the greater of the V1 and V2 inputs
for these options, the V2 pin should be bypassed to GND
with a 0.1F (or greater) capacitor for the LTC2911-1. The
V2 pin of the LTC2911-5 is a high impedance input with a
0.5Vthreshold,allowingthetripthresholdofthemonitored
supply to be configured with a resistive divider.
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