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参数资料
| 型号： | LV5105FN |
| 厂商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC48 |
| 封装： | 7 X 7 MM, VQFN-48 |
| 文件页数： | 5/9页 |
| 文件大小： | 155K |
| 代理商： | LV5105FN |
LV5105FN
No.7600-5/9
Continued from preceding page.
[Input voltage 5 (Vcharge)]
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
H level
VINH5
Input H level
4.4
6
V
L level
VINL5
Input L level
0
3.6
V
[Input voltage 6 (VBATBK)]
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
H level
VINH6
Input H level
REG40
×0.8
VBAT
V
L level
VINL6
Input L level
0
REG40
×0.2
V
Electrical Characteristics : Serial bus
[Serial transfer timing]
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
Cycle time
tcy1
SCLK clock cycle
300
ns
Data setup time 1
ts0
SDEN setup time for rise of SCLK
150
-
ns
Data setup time 2
ts1
SDATA setup time for rise of SCLK
150
-
ns
Data hold time 1
th0
SDEN hold time for fall of SCLK
150
-
ns
Data hold time 2
th1
SDATA hold time for rise of SCLK
150
-
ns
Pulse width 1
tw1L
SCLK L-period pulse width
150
-
ns
Pulse width 2
tw1H
SCLK H-period pulse width
150
-
ns
Pulse width 3
tw2L
SDEN L-period pulse width
1
-
μs
Serial transfer timing conditions
Data length
: 24bit
Clock frequency
: 3MHz or les
"SDATA" is taken in at fall of "SDEN" when "SCLK" of 24 clock is entered during H period of "SDEN."
(Note) "SDATA" is not taken in when "SCLK" is 23 clock or less during H period of "SDEN."
When "SCLOCK" exceeds 25 clock, "SDATA" is taken in at the 24th clock, and subsequent "SDATA" is
ignored.
50%
SDEN
ts0
SCLK
50%
th1
ts1
tw1L
tw1H
tcy1
D3
D2
D1
D0
D15
D13
D14
SDATA
tw2L
A2
A1
A0
A3
A4
A5
A6
A7
Address
Data
th0
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