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参数资料
| 型号： | LV7844DEV-FREQ |
| 厂商： | PLETRONICS INC |
| 元件分类： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 80 MHz - 250 MHz, LVDS OUTPUT |
| 封装： | LEADLESS PACKAGE-4 |
| 文件页数： | 3/8页 |
| 文件大小： | 159K |
| 代理商： | LV7844DEV-FREQ |
LV78D Series 3.3 V
LVDS Clock Oscillators
August 2005
www.pletronics.com
425-776-1880
3
Electrical Specification for 3.30V +
_10% over the specified temperature range
Item
Min
Max
Unit
Condition
Frequency Range
80
250
MHz
Frequency Accuracy “45"
-50
+50
ppm
For all supply voltages, load changes, aging for
1 year, shock, vibration and temperatures
“44"
-25
+25
“20"
-20
+20
Output Waveform
LVDS
Output High Level
--
1.60
Volts
See load circuit
R1 = 50 ohms
Output Low Level
0.90
--
Volts
See load circuit
R1 = 50 ohms
Differential Output (V
OD)
247
454
mVolts
See load circuit
R1 = 50 ohms
Output Offset Voltage (V
OS)
1.125
1.375
Volts
See load circuit
R1 = 50 ohms
Differential Output Error (dV
OS)
--
50
mVolts
See load circuit
R1 = 50 ohms
Output Symmetry
45
55
%
Referenced to 50% of amplitude or crossing
point
Output T
RISE and TFALL
300
700
pS
Vth is 20% and 80% of waveform
Jitter
-
0.15
pS RMS
Measured from 12KHz to 20MHz from Fnominal
-
2.8
Measured from 10Hz to 1MHz from Fnominal
Vcc Supply Current
-
66
mA
Includes current of properly terminated device
Enable/Disable Internal Pull-up
50
-
Kohm
To Vcc (equivalent resistance)
V disable
-
0.8
Volts
Referenced to Ground
V enable
2.0
-
Volts
Referenced to Ground
Output leakage
V
OUT = VCC
-10
+10
uA
Pad 1 low, device disabled
V
OUT = 0V
-10
+10
uA
Enable
-
10
nS
Time for output to reach a logic state
Disable time
-
10
nS
Time for output to reach a high Z state
Start up time
-
5
mS
Measured from the time Vcc = 3.0V
Operating Temperature Range
0
+70
oC
Standard Temperature Range
-40
+85
oC
Extended Temperature Range
“E” Option
Storage Temperature Range
-55
+125
oC
Standby Current I
CC
-
3
uA
Pad 1 low, device disabled
Specifications with Pad 1 E/D open circuit
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