参数资料
型号: LXT361PE
英文描述: Telecommunication IC
中文描述: 通信集成电路
文件页数: 42/52页
文件大小: 1187K
代理商: LXT361PE
LXT361
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
42
Datasheet
Table 31. Receive Timing Characteristics for T1 Operation
(See
Figure 15
)
Parameter
Sym
Min
Typ
1
Max
Unit
Receive clock duty cycle
2, 3
RLCKd
40
50
60
%
Receive clock pulse width
2, 3
t
PW
648
ns
Receive clock pulse width high
t
PWH
324
ns
Receive clock pulse width low
1,3
t
PWL
260
324
388
ns
RPOS/RNEG to RCLK rising time
t
SUR
274
ns
RCLK rising to RPOS/RNEG hold time
t
HR
274
ns
1. Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles
are for worst case jitter conditions.
3. Worst case conditions guaranteed by design only.
Table 32. Receive Timing Characteristics for E1 Operation
(See
Figure 15
)
Parameter
Sym
Min
Typ
1
Max
Unit
Receive clock duty cycle
2, 3
RLCKd
40
50
60
%
Receive clock pulse width
2, 3
t
PW
488
ns
Receive clock pulse width high
t
PWH
244
ns
Receive clock pulse width low
1,3
t
PWL
195
244
293
ns
RPOS/RNEG to RCLK rising time
t
SUR
194
ns
RCLK rising to RPOS/RNEG hold time
t
HR
194
ns
1. Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles
are for worst case jitter conditions (0.4 UI clock displacement for 1.544 MHz.)
3. Worst case conditions guaranteed by design only.
Figure 15. Receive Clock Timing
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LXT362LE PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
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