参数资料
型号: M-986-1R2PL
厂商: CLARE INC
元件分类: 信令电路
英文描述: MFC Transceivers
中文描述: TELECOM, MF SIGNALING CIRCUIT, PQCC44
封装: PLASTIC, LCC-44
文件页数: 6/13页
文件大小: 520K
代理商: M-986-1R2PL
Configuration Bytes
Configuration Byte 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
ECLK
IOM
ENC1
EOD1
CMP1
FB1
ECLK
Channels 1 & 2
1 = External codec clock; 0 = Internal codec clock
IOM
Channels 1 & 2
1 = Binary input/output; 0 = 2-of-6 input/output
ENC1
Channel 1
1 = Enable channel; 0 = Disable channel
EOD1
Channel 1
1 = Indicate end of digit; 0 = No end of digit indication
CMP1
Channel 1
1 = Automatic Compelled mode; 0 = Manual mode
FB1
Channel 1
1 = Forward mode (Tx forward frequencies and Rx backward frequencies)
0 = Backward mode (Tx backward frequencies and Rx forward frequencies)
Configuration Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
ENC2
EOD2
CMP2
FB2
ENC2
Channel 2
1 = Enable channel; 0 = Disable channel
EOD2
Channel 2
1 = Indicate end of digit; 0 = No end of digit indication
CMP2
Channel 2
1 = Automatic Compelled mode; 0 = Manual mode
FB2
Channel 2
1 = Forward mode (Tx forward frequencies and Rx backward frequencies)
0 = Backward mode(Tx backward frequencies and Rx forward frequencies)
www.clare.com
2
M-986-2R2
Rev. 3
Function Description
The M-986 can be set up for various operating modes
by writing two configuration bytes to the coprocessor
port.
Configuration Options
External/Internal Codec Clock (ECLK): If external
codec clocking is selected, an external clocking source
provides an 8kHz transmit framing clock and an 8kHz
receive framing clock. It also provides a serial bit clock
with a frequency that is a multiple of 8 kHz between
2.496 MHz and 216 kHz for exchange of data via the
serial ports. When internal codec clocking is selected,
the M-986 provides an 8kHz framing clock and a 2.048
MHz serial bit clock.
Binary/2 of 6 Input/Output (IOM): When the 2-of-6
input/output is selected, the M-986 encodes the
received R2 MF tone pair into in a 6-bit format, where
each bit represents one of the six possible frequencies.
A logic high level indicates the presence of a frequen-
cy. The digital input to the M-986 that selects the trans-
mitted R2 MF tone pair must also be coded in the
2-of-6 format.
When binary input/output is selected, the M-986
encodes the received R2 MF tone pair into a 4 bit bina-
ry format. The digital input to the M-986 that selects the
transmitted R2 MF tone pair must also be coded in a 4
bit binary format.
Enable/Disable Channel (ENC): When a channel is
disabled, the receiver does not process its codec input
for R2 MF tones, and the transmitter does not respond
to transmit commands. If a transmit command is given
while the channel is enabled, the “tone off” command
must be given before the channel is disabled.
Disabling the channel does not automatically shut off
the transmitter. When a channel is enabled, the receiv-
er and transmitter for that channel function normally.
End-of-Digit Indication (EOD): The end-of-digit indica-
tion option configures the M-986 to inform the host
processor when the far end terminates transmission of
the R2 MF tone it is sending. If this option is disabled,
the host processor will not be notified when tone
transmission terminates.
Automatic Compelled/Manual Sequence Signaling
(CMP): When manual mode is selected, R2 MF tone
transmission is turned on and off only via command
from the host processor.
If the automatic mode is selected, the transmitter and
receiver perform the compelled signaling handshake
automatically. The specifics of operation are different
for the forward and backward configurations.
In forward mode, the transceiver can exist in two
states, STATE 1 and STATE 2:
STATE 1: No backward signal detected.
Transmitter under control of the host.
STATE 2: Backward signal detected.
Transmitter off unconditionally.
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