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参数资料
型号： M2061-13-672.1600LF
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 数字传输电路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36
封装： 9 X 9 MM, CERAMIC, LCC-36
文件页数： 6/12页
文件大小： 477K
代理商： M2061-13-672.1600LF
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
3 of 12
Revised 30Jul2004
Integr ated Circuit Systems , Inc. ● Netw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (5 08) 85 2-54 00
M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Preliminar y In f o r m atio n
Integrated
Circuit
Systems, Inc.
DETAILED BLOCK DIAGRAM
Figure 3: Detailed Block Diagram
DIVIDER SELECTION TABLES
Mfin Divider Look-Up Tables (LUT)
The FIN_SEL1:0 pins select the feedback divider value
(“Mfin”), which sets the overall PLL ratio range. Since
the VCSO frequency is fixed, this allows input reference
selection. The look-up tables vary by device variant.
M2060/61/62: Mfin Value LUT (Includes Divide by 32)
M2065/66/67: Mfin Value LUT (Includes Divide by 16)
Mfec and Rfec Divider Look-Up Tables (LUTs)
The FEC_SEL pins select the Mfec/Rfec divider ratio. The
look-up tables vary by device variant. The Mfec and
Rfec values also establish phase detector frequency.
A lower phase detector frequency improves jitter
tolerance and lowers loop bandwidth.
M2060/65: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)
M2061/66: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)
Use this option for either OTU1 or OTU2 de-mapping
applications, but not both.
Phase
Locked
Loop
(PLL)
M2060 Series
SAW Delay Line
Phase
Shifter
VCSO
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
Phase
Detector
Loop Filter
Amplifier
External
Loop Filter
Components
FOUT0
nFOUT0
FEC_SEL1:0
FIN_SEL1:0
Rfec
Div
MUX
0
REF_SEL
DIF_REF0
nDIF_REF0
1
Mfin Divider
LUT
Mfin Divider
1,4,8,32 Options
Mfec Div
FOUT1
nFOUT1
P Divider
1,4,8,32
Options
P_SEL2:0
NBW
R
IN
R
IN
Mfec/Rfec Divider
LUT
DIF_REF1
nDIF_REF1
LOL
HS with Phase Build-out Opt.
Hitless Switching (HS) Opt.
P Divider
LUT
TriState
FIN_SEL1:0
Mfin
Value
Sample Input Reference Freq. (MHz) Options
For M20601, M2061 & M20622
Note 1: For M2060 with Fvcso = 666.5143 or 669.3266
Note 2: For M2061 and M2062 with Fvcso = 622.0800.
0 0
32
19.44
0 1
8
77.76
10
4
155.52
11
1
622.08
Table 3: M2060/61/62: Mfin Value LUT (Includes Divide by 32)
FIN_SEL1:0
Mfin
Value
Sample Input Reference Freq. (MHz) Options
For M20651, M2066 & M20672
Note 1: For M2065 with Fvcso = 666.5143 or 669.3266
Note 2: For M2066 and M2067 with Fvcso = 622.0800.
0 0
16
38.88
0 1
8
77.76
10
4
155.52
11
1
622.08
Table 4: M2065/66/67: Mfin Value LUT (Includes Divide by 16)
FEC_SEL1:0
1
0
Mfec Rfec
Description
Base Input
Rate (MHz)
Fvcso =
Base Output
Rate (MHz)
For M2060 or M2065 with Fvcso = 666.5143 (OTU1 FEC rate):
0
15 14 255/238 OC-48 to OTU1 encode
622.08
666.5143
0
1
15 15 OTU1 repeater or jitter attenuator
666.5143 666.5143
For M2060 or M2065 with Fvcso = 669.3266 (OTU2 FEC rate):
1
0
85 79 255/237 OC-192 to OTU2 encode
622.08
669.3266
1
85 85 OTU2 repeater or jitter attenuator
669.3266 669.3266
Table 5: M2060/65: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)
FEC_SEL1:0
1
0
Mfec Rfec
Description
Base Input
Rate (MHz)
Fvcso =
Base Output
Rate (MHz)
For M2061 or M2066 with Fvcso = 622.08 (OTU1 or OTU2 FEC rate):
0
79 85 237/255 OTU2 to OC-192 decode 669.3266
622.08
0
1
79 79 OC-192 repeater or jitter attenuator
622.08
1
0
14 15 238/255 OTU1 to OC-48 decode 666.5143
622.08
1
14 14 OC-48 repeater or jitter attenuator
622.08
Table 6: M2061/66: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)
相关PDF资料
PDF描述
M2061-13-672.1600 ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36
M2061-13-690.5692LF ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36
M2061-13-690.5692 ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36
M2061-13I622.0800LF ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36
M2061-13I622.0800 ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36
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