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| 型号： | M2061-13I622.0800LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36 |
| 封装： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件页数： | 1/12页 |
| 文件大小： | 477K |
| 代理商： | M2061-13I622.0800LF |
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
Revised 30Jul2004
Integr a t ed Cir cui t S ystems , Inc . ● N e tw or kin g & C o mm un icat ion s ● www. icst.com ● te l (5 08 ) 85 2-5 4 0 0
M2060/61/62
M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Prelimina r y Inf o r m ation
GENERAL DESCRIPTION
The M2060/61/62 and M2065/66/67 are VCSO (Voltage
Controlled SAW Oscillator) based
clock PLLs designed for FEC clock
ratio translation in 10Gb optical
systems such as OC-192 or 10GbE.
They support FEC (Forward Error
Correction) clock multiplication
ratios, both forward (mapping) and
inverse (de-mapping). Multiplication ratios are
pin-selected from pre-programming look-up tables.
FEATURES
◆ Integrated SAW delay line; Output of 15 to 700 MHz *
◆ Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆ Pin-selectable PLL divider ratios support FEC ratios
M2060/65: OTU1 (255/238) and OTU2 (255/237) Mapping
M2061/66: OTU1 (238/255) or OTU2 (237/255) De-mapping
M2062/67: OTU1 (238/255) and OTU2 (237/255) De-mapping
◆ LVPECL clock output (CML and LVDS options available)
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆ Loss of Lock (LOL) output pin
◆ Narrow Bandwidth control input (NBW pin) to adjust
loop bandwidth
◆ Hitless Switching (HS) options with or without Phase
Build-out (PBO) available to enable SONET (GR-253)
/SDH (G.813) MTIE and TDEV compliance during
reference clock reselection
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Example I/O Clock Frequency Combinations
Using M2061-11-622.0800 FEC De-Map Ratios
FEC De-Map
PLL Ratio
Mfec / Rfec
Base Input Rate 1
(MHz)
Note 1: Input reference clock can be the base frequency shown
Output Clock
(either output)
MHz
1/1
622.0800
622.08
or
155.52
237/255
666.5143
238/255
669.3266
FIN_SEL1:0
P_SEL2:0
Loop
Filter
FEC_SEL1:0
M2060/61/62 VCSO FEC PLL for SONET/OTN
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