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参数资料
| 型号： | M29DW323DB70N1F |
| 厂商： | 意法半导体 |
| 英文描述： | 32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block 3V Supply Flash Memory |
| 中文描述： | 32兆位4Mb的x8或功能的2Mb x16插槽，双行8时24分，启动块3V电源快闪记忆体 |
| 文件页数： | 13/49页 |
| 文件大小： | 818K |
| 代理商： | M29DW323DB70N1F |
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M29DW323DT, M29DW323DB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby.
The Dual Bank architecture of the M29DW323 al-
lows read/write operations in Bank A, while read
operations are being executed in Bank B or vice
versa. Write operations are only allowed in one
bank at a time.
See Tables 3 and 4, Bus Operations, for a summa-
ry. Typically glitches of less than 5ns on Chip En-
able or Write Enable are ignored by the memory
and do not affect bus operations.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
IL
, to Chip Enable
and Output Enable and keeping Write Enable
High, V
IH
. The Data Inputs/Outputs will output the
value, see Figure 12, Read Mode AC Waveforms,
and Table 13, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
IH
, during the whole Bus
Write operation. See Figures 13 and 14, Write AC
Waveforms, and Tables 14 and 15, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
IH
.
Standby.
When Chip Enable is High, V
IH
, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
CC2
, Chip Enable should
be held within V
CC
± 0.2V. For the Standby current
level see Table 12, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
CC3
, for Program or Erase operations un-
til the operation completes.
Automatic Standby.
If CMOS levels (V
CC
± 0.2V)
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
CC2
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V
ID
to be applied to some pins.
Electronic Signature.
The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3 and 4, Bus Operations.
Block Protect and
Chip Unprotect.
Groups
blocks can be protected against accidental Pro-
gram or Erase. The Protection Groups are shown
in Appendix A, Tables 21 and 22, Block Address-
es. The whole chip can be unprotected to allow the
data inside the blocks to be changed.
The V
PP
/Write Protect
pin can be used to protect
the two outermost boot blocks. When V
PP
/Write
Protect
is at V
IL
the two outermost boot blocks are
protected and remain protected regardless of the
Block Protection Status or the Reset/Block Tem-
porary Unprotect pin status.
Block Protect and Chip Unprotect operations are
described in Appendix D.
of
相关PDF资料 |
PDF描述 |
|---|---|
| M29DW323DB70N1E | CABLE ASSEMBLY; LEAD-FREE SOLDER; SMB PLUG TO SMB JACK BULKHEAD; 50 OHM, RG174A/U COAX; 12" CABLE LENGTH; |
| M29DW323DB70N1 | Switch Contact Block; Circuitry:DPST-1NO/1NC; Contact Current Max:10A; Switch Terminals:Solder Lug; Supply Voltage:600VAC |
| M29DW324DT70ZE6E | 32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 16:16, Boot Block 3V Supply Flash Memory |
| M29DW324DB70ZE6E | 32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 16:16, Boot Block 3V Supply Flash Memory |
| M29DW324DT90ZE6E | 32 Mbit 4Mb x8 or 2Mb x16, Dual Bank 16:16, Boot Block 3V Supply Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M29DW323DB70N1T | 制造商:NUMONYX 制造商全称:Numonyx B.V 功能描述:32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block) 3V Supply Flash Memory |
| M29DW323DB70N3E | 制造商:Micron Technology Inc 功能描述:AUTOMOTIVE, PARALLEL NOR, 32MB, TSOP - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 32MBIT 70NS 48TSOP |
| M29DW323DB70N6 | 功能描述:闪存 32M (4Mx8 or 2Mx16) RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| M29DW323DB70N6E | 功能描述:闪存 4Mx8 or 2Mx16 70ns RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| M29DW323DB70N6E | 制造商:Micron Technology Inc 功能描述:FLASH BOTTOM BLOCK 32MB 29DW323 |
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