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参数资料
型号： M29DW640D70ZA1
厂商： 意法半导体
英文描述： 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
中文描述： 64兆位（8兆x8或4Mb的x16插槽，多行，页，引导块）3V电源快闪记忆体
文件页数： 13/56页
文件大小： 942K
代理商： M29DW640D70ZA1
13/56
M29DW640D
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read (Random and
Page modes), Bus Write, Output Disable, Standby
and Automatic Standby.
Using the multiple bank architecture of the
M29DW640D, while programming or erasing is
underway in one group of banks (from 1 to 3),
reading can be conducted in any of the other
banks. Write operations are only allowed in one
bank at a time.
See Tables
3
and
4
, Bus Operations, for a summa-
ry. Typically glitches of less than 5ns on Chip En-
able, Write Enable, and Reset pins are ignored by
the memory and do not affect bus operations.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. To speed up the read operation
the memory array can be read in Page mode
where data is internally read and stored in a page
buffer. The Page has a size of 4 Words and is ad-
dressed by the address inputs A0-A1.
A valid Bus Read operation involves setting the
desired address on the Address Inputs, applying a
Low signal, V
IL
, to Chip Enable and Output Enable
and keeping Write Enable High, V
IH
. The Data In-
puts/Outputs will output the value, see
Figure
11., Random Read AC Waveforms
,
Figure
12., Page Read AC Waveforms
, and
Table
15., Read AC Characteristics
, for details of when
the output becomes valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
IH
, during the whole Bus
Write operation. See Figures
13
and
14
, Write AC
Waveforms, and Tables
16
and
17
, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
IH
.
Standby.
When Chip Enable is High, V
IH
, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
CC2
, Chip Enable should
be held within V
CC
± 0.2V. For the Standby current
level see
Table 14., DC Characteristics
.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
CC3
, for Program or Erase operations un-
til the operation completes.
Automatic Standby.
If CMOS levels (V
CC
± 0.2V)
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
CC2
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V
ID
to be applied to some pins.
Electronic Signature.
The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables
3
and
4
, Bus Operations.
Block Protect and
Chip Unprotect.
Groups of
blocks can be protected against accidental Pro-
gram or Erase. The Protection Groups are shown
in Appendix
A
,
Table 23., Block Addresses
The
whole chip can be unprotected to allow the data in-
side the blocks to be changed.
The V
PP
/Write Protect
pin can be used to protect
the four outermost boot blocks. When V
PP
/Write
Protect
is at V
IL
the four outermost boot blocks
are protected and remain protected regardless of
the Block Protection Status or the Reset/Block
Temporary Unprotect pin status.
Block Protect and Chip Unprotect operations are
described in Appendix
D
.
相关PDF资料
PDF描述
M29DW640D70N6T 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D70N6F 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D70N6E 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D70N6 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D70N1T 64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
相关代理商/技术参数
参数描述
M29DW640D70ZA1E 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D70ZA1F 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D70ZA1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D70ZA6 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640D70ZA6E 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
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