参数资料
型号: M29DW640D90ZA6F
厂商: 意法半导体
英文描述: Dual JFET-Input High-Output-Drive uPower Operational Amplifier 8-SOIC
中文描述: 64兆位(8兆x8或4Mb的x16插槽,多行,页,引导块)3V电源快闪记忆体
文件页数: 17/56页
文件大小: 942K
代理商: M29DW640D90ZA6F
17/56
M29DW640D
The fifth bus cycle latches the Address and the
Data of the fourth Byte to be written.
The sixth bus cycle latches the Address and
the Data of the fifth Byte to be written.
The seventh bus cycle latches the Address
and the Data of the sixth Byte to be written.
The eighth bus cycle latches the Address and
the Data of the seventh Byte to be written.
The ninth bus cycle latches the Address and
the Data of the eighth Byte to be written and
starts the Program/Erase Controller.
Only one bank can be programmed at any one
time. The other bank must be in Read mode or
Erase Suspend.
Fast programming should not be attempted when
V
PP
is not at V
PPH
.
After programming has started, Bus Read opera-
tions in the Bank being programmed output the
Status Register content, while Bus Read opera-
tions to the other Bank output the contents of the
memory array.
Programming can be suspended and then re-
sumed by issuing a Program Suspend command
and a Program Resume command, respectively.
(See
Program Suspend Command
and
Program
Resume Command
paragraphs.)
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg-
ister. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
Note that the Fast Program commands cannot
change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Typical Program times are given in
Table
7., Program, Erase Times and Program, Erase
Endurance Cycles
.
Unlock Bypass Command
The Unlock Bypass command is used in conjunc-
tion with the Unlock Bypass Program command to
program the memory faster than with the standard
program commands. When the cycle time to the
device is long, considerable time saving can be
made by using these commands. Three Bus Write
operations are required to issue the Unlock By-
pass command.
Once the Unlock Bypass command has been is-
sued the bank enters Unlock Bypass mode. The
Unlock Bypass Program command can then be is-
sued to program addresses within the bank, or the
Unlock Bypass Reset command can be issued to
return the bank to Read mode. In Unlock Bypass
mode the memory can be read as if in Read mode.
When V
PP
is applied to the V
PP
/Write Protect pin
the memory automatically enters the Unlock By-
pass mode and the Unlock Bypass Program com-
mand can be issued immediately.
Unlock Bypass Program Command
The Unlock Bypass Program command can be
used to program one address in the memory array
at a time. The command requires two Bus Write
operations, the final write operation latches the ad-
dress and data in the internal state machine and
starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. The
operation cannot be aborted, a Bus Read opera-
tion to the Bank where the command was issued
outputs the Status Register. See the Program
command for details on the behavior.
Unlock Bypass Reset Command
The Unlock Bypass Reset command can be used
to return to Read/Reset mode from Unlock Bypass
Mode. Two Bus Write operations are required to
issue the Unlock Bypass Reset command. Read/
Reset command does not exit from Unlock Bypass
Mode.
Chip Erase Command
The Chip Erase command can be used to erase
the entire chip. Six Bus Write operations are re-
quired to issue the Chip Erase Command and start
the Program/Erase Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100μs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands, including the Erase Suspend com-
mand. It is not possible to issue any command to
abort the operation. Typical chip erase times are
given in Table
7
. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the sec-
tion on the Status Register for more details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
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