参数资料
型号: M30201F6FP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP56
封装: PLASTIC, QFP-56
文件页数: 16/28页
文件大小: 2425K
代理商: M30201F6FP
Clock Generating Circuit
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
22
Pin
States
Port
Retains status before wait mode
CLKOUT
When fC selected
Does not stop
When f8, clock devided
Does not stop when the WAIT
counter output selected
peripheral function clock stop bit is “0”.
When the WAIT peripheral function
clock stop bit is “1”,the status immedi-
ately prior to entering wait mode is
maintained.
Wait Mode
When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function
clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral
functions, allowing power dissipation to be reduced. However, peripheral function clock fC32 does not stop
so that the peripherals using fC32 do not contribute to the power saving. When the MCU running in low-
speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”. Table 1.4 shows the
status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the
WAIT instruction was executed.
Table 1.4. Port status during wait mode
Table 1.3. Port status during stop mode
Stop Mode, Wait Mode
Pin
States
Port
Retains status before stop mode
CLKOUT
When fC selected
“H”
When f8, clock devided
Retains status before stop mode
counter output selected
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains
above 2V.
Because the oscillation of BCLK, f1 to f32, fc, fc32, and fAD stops in stop mode, peripheral functions such as
the A-D converter and watchdog timer do not function. However, timer A, timer B and timer X operate
provided that the event counter mode is set to an external pulse, and UART0 functions provided an external
clock is selected. Table 1.3 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
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