参数资料
型号: M30600E8-XXXGP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件页数: 78/139页
文件大小: 1782K
代理商: M30600E8-XXXGP
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
43
Interrupt
Change of IPL
Reset
Level 0 (“0002”) is set
_______
NMI
Level 7 (“1112”) is set
________
DBC
Does not change
Watchdog timer
Level 7 (“1112”) is set
Single step
Does not change
Address match
Does not change
Software interrupt
Does not change
(3) Flag changes
When an interrupt request is received, the stack pointer select flag (U flag) changes to “0” and the flag
register (FLG) and program counter (PC) are saved to the stack area indicated by the interrupt stack
pointer (ISP). Thereafter, the interrupt enable flag (I flag) and debug flag (D flag) change to “0” and the
processor interrupt priority level (IPL) at the flag register (FLG) is replaced by the priority level of the
received interrupt. However, when interrupt requests are received for software interrupt Nos. 32 to 63, the
flag register (FLG) and program counter (PC) are saved to the stack shown by the stack pointer select
flag (U flag) at the time the interrupt was received. The stack pointer select flag (U flag) does not change.
The value of the processor interrupt priority level (IPL) in the flag register (FLG) differs in the case of
_______ ________
reset, NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and undefined
instruction interrupts. Table 1.19 shows how the IPL changes when interrupt requests are received.
Table 1.19. Change of IPL state when interrupt requests are accepted
Interrupts
相关PDF资料
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M30600E8GP 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP100
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