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参数资料
| 型号： | M30624FGPFP-D5 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件页数： | 16/87页 |
| 文件大小： | 919K |
| 代理商： | M30624FGPFP-D5 |
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M16C/62P Group (M16C/62P, M16C/62PT)
page 23
2. Central Processing Unit (CPU)
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2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is cleared to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write “0”. When read, its content is indeterminate.
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相关代理商/技术参数 |
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| M30624FGPFPU5C | 制造商:Renesas Electronics Corporation 功能描述:MCU,M16C/62P Group (M16C/62P, M16C/62PT) |
| M30624FGPGP | 制造商:Renesas Electronics Corporation 功能描述:Micro,M16C/62P,ROM 256k+4k FL, |
| M30624FGPGP D5 | 制造商:Renesas Electronics Corporation 功能描述: |
| M30624FGPGP#D3 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16-Bit/32-Bit M16C CISC 256KB Flash 3.3V/5V 100-Pin LQFP 制造商:Renesas Electronics Corporation 功能描述:MCU 16BIT R8C CISC 256KB FLASH 3.3V/5V 100LQFP - Trays |
| M30624FGPGP#D3C | 功能描述:IC M16C MCU FLASH 256K 100-LQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:M16C™ M16C/60/62P 产品培训模块:CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 M16C Product Overview Part 1 M16C Product Overview Part 2 标准包装:1 系列:M16C™ M32C/80/87 核心处理器:M32C/80 芯体尺寸:16/32-位 速度:32MHz 连通性:EBI/EMI，I²C，IEBus，IrDA，SIO，UART/USART 外围设备:DMA，POR，PWM，WDT 输入/输出数:121 程序存储器容量:384KB（384K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:24K x 8 电压 - 电源 (Vcc/Vdd):3 V ~ 5.5 V 数据转换器:A/D 34x10b，D/A 2x8b 振荡器型:内部 工作温度:-20°C ~ 85°C 封装/外壳:144-LQFP 包装:托盘 产品目录页面:749 (CN2011-ZH PDF) 配用:R0K330879S001BE-ND - KIT DEV RSK M32C/87 |
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