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参数资料
| 型号： | M312L2923BG0-CB3 |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | TVS 1500W 15V UNIDIRECT SMC |
| 中文描述： | DDR SDRAM的注册模块 |
| 文件页数： | 12/18页 |
| 文件大小： | 274K |
| 代理商： | M312L2923BG0-CB3 |
DDR SDRAM
1GB, 2GB Registered DIMM
Rev. 1.1 August. 2003
AC Timming Parameters & Specifications
Parameter
Sym-
bol
B3
(DDR333@CL=2.5))
Min
A2
(DDR266@CL=2)
Min
B0
(DDR266@CL=2.5)
Min
Uni
t
Note
Max
Max
Max
Row cycle time
tRC
60
65
65
ns
Refresh row cycle time
tRFC
72
75
75
ns
Row active time
tRAS
42
70K
45
120K
45
120K
ns
RAS to CAS delay
tRCD
18
20
20
ns
Row precharge time
tRP
18
20
20
ns
Row active to Row active
tRRD
12
15
15
ns
Write recovery time
tWR
15
15
15
ns
Last data in to Read com-
mand
tWTR
1
1
1
tCK
Col. address to Col. address
tCCD
1
1
1
tCK
Clock cycle time
CL=2.0
tCK
7.5
12
7.5
12
10
12
ns
CL=2.5
6
12
7.5
12
7.5
12
ns
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS-out access time from
tDQSCK
-0.6
+0.6
-0.75
+0.75
-0.75
+0.75
ns
Output data access time
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput
tDQSQ
-
0.4
-
0.5
-
0.5
ns
12
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRE
0
0
0
ns
3
DQS-in hold time
tWPRE
0.25
0.25
0.25
tCK
DQS falling edge to CK ris-
tDSS
0.2
0.2
0.2
tCK
DQS falling edge from CK
tDSH
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
tCK
DQS-in cycle time
tDSC
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Address and Control Input
tIS
0.75
0.9
0.9
ns
i,5.7~
Address and Control Input
tIH
0.75
0.9
0.9
ns
i,5.7~
Address and Control Input
tIS
0.8
1.0
1.0
ns
i, 6~9
Address and Control Input
tIH
0.8
1.0
1.0
ns
i, 6~9
Data-out high impedence
time from CK/CK
tHZ
+0.7
+0.75
+0.75
ns
1
Data-out low impedence
time from CK/CK
tLZ
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
1
Input Slew Rate(for input
tSL(I)
0.5
0.5
0.5
V/
Input Slew Rate(for I/O pins)
tSL(IO)
0.5
0.5
0.5
V/
ns
Output Slew Rate(x4,x8)
tSL(O)
1.0
4.5
1.0
4.5
1.0
4.5
V/
Output Slew Rate Matching
tSLMR
0.67
1.5
0.67
1.5
0.67
1.5
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