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参数资料
| 型号： | M32182F8VFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封装： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件页数： | 17/36页 |
| 文件大小： | 292K |
| 代理商： | M32182F8VFP |
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2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group
Under Development
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
24
12-channel A-D Converters
The microcomputer contains 12-channel A-D converters
with 10-bit resolution. In addition to single conversion on
each channel, continuous A-D conversion on a combined
group of N (N = 1–12) channels is possible. The A-D con-
verted value can be read out in either 10-bit or 8-bit.
In addition to ordinary A-D conversion, the converters sup-
port comparator mode in which the set value and A-D con-
verted value are compared to determine which is larger or
smaller than the other.
Moreover, there is also Sample & hold function, input volt-
age is sampled, when A-D conversion is started, and the A-
D conversion of the sampling voltage is carried out.
Since there is no invalid domain near [which becomes a prob-
lem by the external operational amplifier etc.] VCCE/VSS, con-
version by the full range is possible in this sample & hold circuit.
When A-D conversion is finished, the converters can gen-
erate a DMA transfer request, as well as an interrupt.
The A-D converters are interfaced using a dedicated power
supply to allow for connections to the peripheral circuits
operating with 5 V.
Table 6. Outline of the A-D Converters
Item
Content
Analog input
12-channel
A-D conversion method
Successive approximation method
Resolution
10-bit (Conversion results can be read out in either 10 or 8-bit)
During low speed mode: Normal mode: + 2 LSB, double speed mode: + 2 LSB (Note 1)
Absolute accuracy (conditions:
Ta = 25°C, AVCC0, 1 =
VREF0, 1 = 5.12 V)
During high speed mode: Normal mode: + 3 LSB, double speed mode: + 3 LSB (Note 1)
Conversion mode
A-D conversion mode, comparator mode
Operation mode
Single mode, scan mode
Scan mode
Single-shot scan mode, continuous scan mode
Special mode
Single mode forcible execution under scan mode operation, scan mode start after the sin-
gle mode execution, conversion re-start
Sample & hold function
Input voltage is sampled when A-D conversion is started, and it is A-D conversion about
sampling voltage.
Software start
Started by setting A-D conversion start bit to 1
Conversion start trigger
Hardware start
MJT input event bus 2, MJT input event bus 3, MJT output
event bus 3, and TIN23
Low-speed
mode
Normal
299
×1/f(BCLK) (Note 2)
Double speed
173
×1/f(BCLK)
High-speed
mode
Normal
131
×1/f(BCLK)
During single mode
(Unavailable for Sample
& Hold
Available for Normal
Sample & Hold)
Double speed
89
×1/f(BCLK)
Low-speed
mode
Normal
191
×1/f(BCLK)
Double speed
101
×1/f(BCLK)
High-speed
mode
Normal
95
×1/f(BCLK)
During single mode
(Available for High-speed
Sample & Hold)
Double speed
53
×1/f(BCLK)
Low-speed
mode
Normal
47
×1/f(BCLK)
Double speed
29
×1/f(BCLK)
High-speed
mode
Normal
23
×1/f(BCLK)
Conversion Speed
f(BCLK) : Internal peripheral
clock operating frequency
During comparator mode
Double speed
17
×1/f(BCLK)
When A-D conversion is finished, when comparate operation is finished
Interrupt request generation
When single-shot scan is finished, or when one cycle of continuous scan is finished
When A-D conversion is finished, when comparate operation is finished
DMA transfer request genera-
tion
When single-shot scan is finished, or when one cycle of continuous scan is finished
Note 1: The performance is the same during sample & hold function.
Note 2: When XIN = 10 MHz, f(BLCK) = 20 MHz.
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