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参数资料
| 型号： | M32182F8VFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封装： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件页数： | 19/36页 |
| 文件大小： | 292K |
| 代理商： | M32182F8VFP |
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2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group
Under Development
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
26
4-channel High-speed Serial I/Os
The microcomputer contains 4 channels of serial I/Os
consisting of four channels that can be set for CSIO mode
(clock-synchronized serial I/O) or UART mode (asynchro-
nous serial I/O) and two other channels that can only be
set for UART mode.
The SIO has the function to generate a DMA transfer re-
quest when data reception is completed or the transmit
register becomes empty, and is capable of high-speed
serial communication without causing any additional CPU
load.
Table 7. Outline of the Serial I/O
Item
Content
Number of channels
CSIO/UART: 2 channels (SIO0, SIO1)
UART only : 2 channels (SIO2, SIO3)
Clock
During CSIO mode : Internal clock / external clock, selectable
(Note 1)
During UART mode: Internal clock only
Transfer mode
Transmit half-duplex, receive half-duplex, transmit/receive full-duplex
BRG count source
f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BCLK)/256 (When internal clock is selected)
(Note 2)
Data format
CSIO mode: Data length = Fixed to 8-bit
Order of transfer = Fixed to LSB first
UART mode: Start bit = 1-bit
Character length = 7, 8, or 9-bit
Parity bit = With or without (If included, selectable between odd and even parity)
Stop bit = 1 or 2-bit
Order of transfer = Fixed to LSB first
Baud rate
CSIO mode: 152-bit per second to 2M-bit per second (when operating with f(BCLK) = 20 MHz)
UART mode: 19-bit per second to 156K-bit per second (when operating with f(BCLK) = 20 MHz)
Error detection
CSIO mode: Overrun error only
UART mode: Overrun, parity, and framing errors
(The error-sum bit indicates which error has occurred)
Fixed cycle clock output
function
When SIO0 or SIO1 is in UART mode, this function outputs a 1/2 BRG clock from the SCLK pin.
Note 1: During CSIO mode, the maximum input frequency of an external clock is f(BCLK) divided by 16.
Note 2: When f(BCLK) is selected for the BRG count source, the BRG set value is subject to limitations.
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