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参数资料
| 型号： | M34250E2-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, OTPROM, 4.4 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | PLASTIC, SOP-20 |
| 文件页数： | 18/61页 |
| 文件大小： | 654K |
| 代理商： | M34250E2-XXXFP |
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22
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Table 10 Control registers related to timer
V13
V12
V11
V10
Timer control register V1
Port G1 (I/O)
TOUT pin (output)/port G1(input)
Prescaler stop (initial state) / timer 1 stop (state retained)
Prescaler / timer 1 operation
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
0
1
0
1
0
1
0
1
G1/TOUT pin function selection bit
Prescaler/timer 1 operation start bit
Timer 1 interrupt enable bit
External interrupt enable bit
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Set a value to the bit 2 of register K0, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least
one instruction. According to the input state of G0/INT pin, the external interrupt request flag (EXF0) may be set to “1” when
the interrupt valid waveform is changed.
at reset : 00002
R/W
at RAM back-up : 00002
K03
K02
K01
K00
Instruction clock divided by 4
Instruction clock divided by 512
Rising waveform (“L”
→ “H”)
Falling waveform (“H”
→ “L”)
Key-on wakeup not used
Key-on wakeup used (“L” level recognized)
Key-on wakeup not used
Key-on wakeup used (“L” level recognized)
Prescaler dividing ratio selection bit
Interrupt valid waveform for INT pin/
key-on wakeup valid waveform selection
bit (Note 2)
Ports G1–G3 key-on wakeup control bit
Ports S0–S3 key-on wakeup control bit
Key-on wakeup control register K0
at reset : 00002
at RAM back-up : state retained
0
1
0
1
0
1
0
1
R/W
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| M34250M2-XXXFP | 4-BIT, MROM, 4.4 MHz, MICROCONTROLLER, PDSO20 |
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