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参数资料
| 型号： | M34508G4-XXXGP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, SSOP-20 |
| 文件页数： | 11/32页 |
| 文件大小： | 1049K |
| 代理商： | M34508G4-XXXGP |
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4508 Group
Rev.1.03
2009.07.27
page 19 of 140
REJ03B0148-0103
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
An interrupt activated condition is satisfied (request flag = “1”)
Interrupt enable bit is enabled (“1”)
Interrupt enable flag is enabled (INTE = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request flag
for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt
enable/disable. Interrupts are enabled when INTE flag is set to “1”
with the EI instruction and disabled when INTE flag is cleared to “0”
with the DI instruction. When any interrupt occurs, the INTE flag is
automatically cleared to “0,” so that other interrupts are disabled un-
til the EI instruction is executed.
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2 to
select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and skip
instruction.
Table 5 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corre-
sponding interrupt request flag is set to “1.” Each interrupt request
flag is cleared to “0” when either;
an interrupt occurs, or
the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition is sat-
isfied even if the interrupt is disabled by the INTE flag or its interrupt
enable bit. Once set, the interrupt request flag retains set until a
clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt dis-
able state is released, the interrupt priority level is as follows shown
in Table 3.
Table 3 Interrupt sources
Activated condition
Level change of INT
pin
Timer 1 underflow
Timer 2 underflow
Completion of
A/D conversion
Completion of serial
interface transmit/
recieve
Priority
level
1
2
3
4
5
Interrupt name
External 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
A/D interrupt
Serial interface
interrupt
Table 5 Interrupt enable bit function
Occurrence of interrupt
Enabled
Disabled
Skip instruction
Invalid
Valid
Interrupt enable bit
1
0
Interrupt
address
Address 0
in page 1
Address 4
in page 1
Address 6
in page 1
Address C
in page 1
Address E
in page 1
Table 4 Interrupt request flag, interrupt enable bit and skip in-
struction
Interrupt
request flag
EXF0
T1F
T2F
ADF
SIOF
Interrupt name
External 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
A/D interrupt
Serial interface
interrupt
Skip instruction
SNZ0
SNZT1
SNZT2
SNZAD
SNZSI
Interrupt
enable bit
V10
V12
V13
V22
V23
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PDF描述 |
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| M34509G4-XXXFP | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M34509G4FP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34509G4HFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34509G4H-XXXFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34509G4-XXXFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34509T2-CPE | 功能描述:DEV TOOL COMPACT EMULATOR: 4508/ RoHS:否 类别:编程器，开发系统 >> 内电路编程器、仿真器以及调试器 系列:- 产品变化通告:Development Systems Discontinuation 19/Jul/2010 标准包装:1 系列:* 类型:* 适用于相关产品:* 所含物品:* |
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