参数资料
型号: M34509G4FP
元件分类: 微控制器/微处理器
英文描述: 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24
封装: 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件页数: 96/145页
文件大小: 1060K
代理商: M34509G4FP
Rev.1.03
2009.07.27
page 52 of 140
REJ03B0147-0103
4509 Group
(4) Return signal
An external wakeup signal is used to return from the RAM back-up
mode because the oscillation is stopped. Table 20 shows the return
condition for each return source.
(5) Control registers
Key-on wakeup control register K0
Register K0 controls the port P0 key-on wakeup function. Set the
contents of this register through register A with the TK0A instruc-
tion. In addition, the TAK0 instruction can be used to transfer the
contents of register K0 to register A.
Key-on wakeup control register K1
Register K1 controls the port P1 key-on wakeup function. Set the
contents of this register through register A with the TK1A instruc-
tion. In addition, the TAK1 instruction can be used to transfer the
contents of register K1 to register A.
Key-on wakeup control register K2
Register K2 controls the ports P2, D2 and D3 key-on wakeup func-
tion. Set the contents of this register through register A with the
TK2A instruction. In addition, the TAK2 instruction can be used to
transfer the contents of register K2 to register A.
Key-on wakeup control register L1
Register L1 controls the selection of the return condition and valid
waveform/level of port P1, and the selection of the INT pin return
condition and INT pin key-on wakeup function. Set the contents of
this register through register A with the TL1A instruction. In addi-
tion, the TAL1 instruction can be used to transfer the contents of
register L1 to register A.
Table 20 Return source and return condition
Remarks
The key-on wakeup function can be selected by one port unit. Set the port
using the key-on wakeup function to “H” level before going into the RAM
back-up state.
The key-on wakeup function can be selected by one port unit. Select the
return level (“L” level or “H” level) and return condition (level or edge) with
the register L1 according to the external state before going into the RAM
back-up state.
Before going into the RAM backup state, set an opposite level of the
selected return level (edge) to the port using the key-on wakeup function.
The key-on wakeup function can be selected by one port unit. Select the
return level (“L” level or “H” level) with the register I1 and return condition
(level or edge) with the register L1 according to the external state before
going into the RAM back-up state.
Return condition
Return by an external “L” level in-
put.
Return by an external “H” level or
“L” level input, or falling edge
(“H”→“L”) or rising edge (“L”→“H”).
Return by an external “H” level or
“L” level input, or falling edge
(“H”→“L”) or rising edge (“L”→“H”).
When the return level is input, the
EXF0 flag is not set.
External
wakeup
signal
Return source
Port P00–P03
Port P20, P21
Port D2, D3
Port P1 0 –P1 3
INT pin
Pull-up control register PU0
Register PU0 controls the ON/OFF of the port P0 pull-up transis-
tor. Set the contents of this register through register A with the
TPU0A instruction. In addition, the TAK1 instruction can be used to
transfer the contents of register K0 to register A.
Pull-up control register PU1
Register PU1 controls the ON/OFF of the port P1 pull-up transis-
tor. Set the contents of this register through register A with the
TPU1A instruction. In addition, the TAPU1 instruction can be used
to transfer the contents of register PU1 to register A.
Pull-up control register PU2
Register PU2 controls the ON/OFF of the ports P2, D2 and D3 pull-
up transistor. Set the contents of this register through register A
with the TPU2A instruction. In addition, the TAPU2 instruction can
be used to transfer the contents of register PU2 to register A.
Interrupt control register I1
Register I1 controls the valid waveform/level of the external 0 inter-
rupt and the input control of INT pin. Set the contents of this
register through register A with the TI1A instruction. In addition, the
TAI1 instruction can be used to transfer the contents of register I1
to register A.
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