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参数资料
| 型号： | M34524MC-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件页数： | 17/66页 |
| 文件大小： | 1936K |
| 代理商： | M34524MC-XXXFP |
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Rev.1.04
Aug 23, 2007
Page 24 of 146
REJ03B0188-0104
4559 Group
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as
follows (Figure 25).
Program counter (PC)
An interrupt address is set in program counter. The address to
b e ex ec u t e d wh e n re t u rn in g to the mai n rout ine is
automatically stored in the stack register (SK).
Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
Interrupt request flag
Only the request flag for the current interrupt source is cleared
to “0”.
Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored
automatically in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is
executed after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an
interrupt address. Use the RTI instruction to return from an
interrupt service routine.
Interrupt enabled by executing the EI instruction is performed
after executing 1 instruction (just after the next instruction is
executed). Accordingly, when the EI instruction is executed just
before the RTI instruction, interrupts are enabled after returning
the main routine. (Refer to Figure 24)
Fig 24. Program example of interrupt processing
Fig 25. Internal state when interrupt occurs
Fig 26. Interrupt system diagram
Main
routine
Interrupt
occurs
Interrupt is
enabled
Interrupt
service routine
EI
RTI
: Interrupt enabled state
: Interrupt disabled state
Each interrupt address
Program counter (PC)
The address of main routine to be
executed when returning
Stack register (SK)
0 (Interrupt disabled)
Interrupt enable flag (INTE)
0
Interrupt request flag (only the flag for the current interrupt
source)
Stored in the interrupt stack register (SDP)
automatically
Data pointer, carry flag, registers A and B, skip flag
Request flag
(state retained)
Enable bit
Enable flag
Timer 2
underflow
T1F
V12
Address 4
in page 1
Timer 1
underflow
T2F
V13
Address 6
in page 1
T3F
V20
Address 8
in page 1
Activated
condition
INTE
Timer 3
underflow
EXF0
V10
Address 0
in page 1
INT pin interrupt
waveform input
相关PDF资料 |
PDF描述 |
|---|---|
| M34524M8-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| M34524EDFP | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| M34551E8-XXXFP | 4-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP48 |
| M34551E8FP | 4-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP48 |
| M34551M4-XXXFP | 4-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP48 |
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