参数资料
型号: M37221M8H-XXXSP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP42
封装: 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件页数: 49/112页
文件大小: 1179K
代理商: M37221M8H-XXXSP
M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Rev.1.00
Oct 01, 2002
page 41 of 110
REJ03B0134-0100Z
8.6.10 Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz with the ACK return mode enable, is
shown below.
Set a slave address in the high-order 7 bits of the I2C address
register (address 00D816) and “0” in the RBW bit.
Set the ACK return mode and SCL = 100 kHz by setting “8516” in
the I2C clock control register (address 00DB16).
Set “1016” in the I2C status register (address 00D916) and hold the
SCL at HIGH.
④ Set a communication enable status by setting “4816” in the I2C
control register (address 00DA16).
Set the address data of the destination of transmission in the high-
order 7 bits of the I2C data shift register (address 00D716) and set
“0” in the least significant bit.
⑥ Set “F016” in the I2C status register (address 00D916) to generate
a START condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
⑦ Set transmit data in the I2C data shift register (address 00D716). At
this time, an SCL and an ACK clock automatically occurs.
When transmitting control data of more than 1 byte, repeat step .
Set “D016” in the I2C status register (address 00D916). After this, if
ACK is not returned or transmission ends, a STOP condition will
be generated.
8.6.11 Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, with the ACK non-return mode enabled
while using the addressing format, is shown below.
Set a slave address in the high-order 7 bits of the I2C address
register (address 00D816) and “0” in the RBW bit.
Set the ACK non-return mode and SCL = 400 kHz by setting “2516
in the I2C clock control register (address 00DB16).
Set “1016” in the I2C status register (address 00D916) and hold the
SCL at HIGH.
④ Set a communication enable status by setting “4816” in the I2C
control register (address 00DA16).
When a START condition is received, an address comparison is
executed.
⑥ When all transmitted address are“0” (general call):
AD0 of the I2C status register (address 00D916) is set to “1” and
an interrupt request signal occurs.
When the transmitted addresses match the address set in :
ASS of the I2C status register (address 00D916) is set to “1” and
an interrupt request signal occurs.
In the cases other than the above:
AD0 and AAS of the I2C status register (address 00D916) are set
to “0” and no interrupt request signal occurs.
⑦ Set dummy data in the I2C data shift register (address 00D716).
When receiving control data of more than 1 byte, repeat step .
When a STOP condition is detected, the communication ends.
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